slight update to interrupts

1 files changed, 33 insertions, 4 deletions

diff --git a/interrupts.h b/interrupts.h
index cf4c8b7..9dacc42 100644
--- a/interrupts.h
+++ b/interrupts.h
@@ -1,8 +1,37 @@
-//
-// Created by vetch on 26.11.19.
-//
-
 #ifndef RPI_MMU_EXAMPLE_INTERRUPTS_H
 #define RPI_MMU_EXAMPLE_INTERRUPTS_H
 
+#include <stdint.h>
+
+    //offset of peripherals+ offset for first addresable register for interupt controller
+#define RPI_INTERRUPT_CONTROLLER_BASE   ( 0x3F000000UL + 0xB200 )
+
+// Bits in the Enable_Basic_IRQs register to enable various interrupts.
+// According to the BCM2835 ARM Peripherals manual, section 7.5 */
+
+#define RPI_BASIC_ARM_TIMER_IRQ         (1 << 0)
+#define RPI_BASIC_ARM_MAILBOX_IRQ       (1 << 1)
+#define RPI_BASIC_ARM_DOORBELL_0_IRQ    (1 << 2)
+#define RPI_BASIC_ARM_DOORBELL_1_IRQ    (1 << 3)
+#define RPI_BASIC_GPU_0_HALTED_IRQ      (1 << 4)
+#define RPI_BASIC_GPU_1_HALTED_IRQ      (1 << 5)
+#define RPI_BASIC_ACCESS_ERROR_1_IRQ    (1 << 6)
+#define RPI_BASIC_ACCESS_ERROR_0_IRQ    (1 << 7)
+
+// @brief The interrupt controller memory mapped register set
+typedef struct {
+    volatile uint32_t IRQ_basic_pending;
+    volatile uint32_t IRQ_pending_1;
+    volatile uint32_t IRQ_pending_2;
+    volatile uint32_t FIQ_control;
+    volatile uint32_t Enable_IRQs_1;
+    volatile uint32_t Enable_IRQs_2;
+    volatile uint32_t Enable_Basic_IRQs;
+    volatile uint32_t Disable_IRQs_1;
+    volatile uint32_t Disable_IRQs_2;
+    volatile uint32_t Disable_Basic_IRQs;
+} rpi_irq_controller_t;
+
+extern rpi_irq_controller_t* RPI_GetIrqController(void);
+
 #endif //RPI_MMU_EXAMPLE_INTERRUPTS_H