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author | Wojtek Kosior <kwojtus@protonmail.com> | 2019-10-07 08:08:22 +0200 |
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committer | Wojtek Kosior <kwojtus@protonmail.com> | 2019-10-07 08:08:22 +0200 |
commit | 9523d2fc13ef8c53cc0753c90293f6b7577e39a5 (patch) | |
tree | 9f14bc49fd778c9b7999961c250b2ffc96a8eeba | |
parent | c0f127091eec7a9c975389fda5f49c63eccb3d3a (diff) | |
download | rpi-MMU-example-9523d2fc13ef8c53cc0753c90293f6b7577e39a5.tar.gz rpi-MMU-example-9523d2fc13ef8c53cc0753c90293f6b7577e39a5.zip |
check paging support in kernel_main()
-rw-r--r-- | kernel.c | 22 |
1 files changed, 21 insertions, 1 deletions
@@ -137,7 +137,27 @@ void kernel_main(uint32_t r0, uint32_t r1, uint32_t atags) uart_init(); uart_puts("Hello, kernel World!\r\n"); - + + uint32_t ID_MMFR0; + // get contents of coprocessor register to check for paging support + asm("mrc p15, 0, %0, c0, c1, 4" : "=r" (ID_MMFR0)); + + char *paging; + + uart_puts("hmmm\n\r"); + + switch(ID_MMFR0 & 7) /* lowest 4 bits indicate VMSA support */ { + case 0 : paging = "no paging\n\r"; break; + case 1 : paging = "implementation defined paging\n\r"; break; + case 2 : paging = "VMSAv6, with cache and TLB type registers\n\r"; break; + case 3 : paging = "VMSAv7, with support for remapping and access flag\n\r"; break; + case 4 : paging = "VMSAv7 with PXN bit supported\n\r"; break; + case 5 : paging = "VMSAv7, PXN and long format descriptors. EPAE is supported.\n\r"; break; + default : paging = "?_? unknown paging ?_?\n\r"; + } + + uart_puts(paging); + while (1) uart_putc(uart_getc()); } |