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authorWojtek Kosior <kwojtus@protonmail.com>2019-12-31 23:12:54 +0100
committerWojtek Kosior <kwojtus@protonmail.com>2019-12-31 23:12:54 +0100
commit13199395faf225fe78d2ef4540ea3e75edb4e640 (patch)
treecb630f7297596eb01cc9d281a2338ff993659335
parent263a2ddec4f7f17c5bcd3a36ded396f6fe4e836a (diff)
downloadrpi-MMU-example-13199395faf225fe78d2ef4540ea3e75edb4e640.tar.gz
rpi-MMU-example-13199395faf225fe78d2ef4540ea3e75edb4e640.zip
GPU clock stuff (probably not to be finished...)
-rw-r--r--bcmclock.h53
1 files changed, 53 insertions, 0 deletions
diff --git a/bcmclock.h b/bcmclock.h
new file mode 100644
index 0000000..7fd192d
--- /dev/null
+++ b/bcmclock.h
@@ -0,0 +1,53 @@
+#ifndef BCMCLOCK_H
+#define BCMCLOCK_H
+
+#include <stdint.h>
+
+#include "global.h"
+
+#define ST_BASE (PERIF_BASE + 0x3000) // System Timer
+
+#define ST_CS (ST_BASE + 0x0) // System Timer Control/Status
+#define ST_CLO (ST_BASE + 0x4) // System Timer Counter Lower 32 bits
+#define ST_CHI (ST_BASE + 0x8) // System Timer Counter Higher 32 bits
+#define ST_C0 (ST_BASE + 0xC) // System Timer Compare 0
+#define ST_C1 (ST_BASE + 0x10) // System Timer Compare 1
+#define ST_C2 (ST_BASE + 0x14) // System Timer Compare 2
+#define ST_C3 (ST_BASE + 0x18) // System Timer Compare 3
+
+// ARM control block
+// called "base address for the ARM interrupt register" elsewhere
+#define ARM_BASE (PERIF_BASE + 0xB000)
+
+#define ARM_IRQ_BASIC_PENDING (ARM_BASE + 0x200)
+#define ARM_IRQ_PENDING_1 (ARM_BASE + 0x204)
+#define ARM_IRQ_PENDING_2 (ARM_BASE + 0x208)
+#define ARM_FIQ_CONTROL (ARM_BASE + 0x20C)
+#define ARM_ENABLE_IRQS_1 (ARM_BASE + 0x210)
+#define ARM_ENABLE_IRQS_2 (ARM_BASE + 0x214)
+#define ARM_ENABLE_BASIC_IRQS (ARM_BASE + 0x218)
+#define ARM_DISABLE_IRQS_1 (ARM_BASE + 0x21C)
+#define ARM_DISABLE_IRQS_2 (ARM_BASE + 0x220)
+#define ARM_DISABLE_BASIC_IRQS (ARM_BASE + 0x224)
+
+
+static inline void enable_timer_irq(void)
+{
+ *(uint32_t volatile*) ARM_ENABLE_BASIC_IRQS = 1;
+ *(uint32_t volatile*) ARM_ENABLE_IRQS_1 = 1 << 2;
+}
+
+static inline void disable_timer_irq(void)
+{
+ *(uint32_t volatile*) ARM_DISABLE_BASIC_IRQS = 1;
+ *(uint32_t volatile*) ARM_DISABLE_IRQS_1 = 1 << 2;
+}
+
+static inline void set_timer_match_timeout(uint32_t timeout)
+{
+ uint32_t clock_now = *(uint32_t volatile*) ST_CLO;
+ *(uint32_t volatile*) ST_C2 = clock_now + timeout;
+ *(uint32_t volatile*) ST_CS = 1 << 2;
+}
+
+#endif // BCMCLOCK_H