From 2a4fa1d127b28b05da08b930456a0c2e44d745c3 Mon Sep 17 00:00:00 2001 From: Josselin Poiret Date: Tue, 21 Mar 2023 09:59:36 +0100 Subject: gnu: opensbi: Build with default gcc, with microarch rv64g. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * gnu/packages/firmware.scm (make-opensbi-package): Remove specific #:xgcc for the cross-toolchain, there is not reason for it now. Also set the microarch to rv64g, so that it builds. Signed-off-by: Ludovic Courtès --- gnu/packages/firmware.scm | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'gnu/packages/firmware.scm') diff --git a/gnu/packages/firmware.scm b/gnu/packages/firmware.scm index 956ece5d6d..0b7fff035a 100644 --- a/gnu/packages/firmware.scm +++ b/gnu/packages/firmware.scm @@ -486,7 +486,7 @@ provide OpenFirmware functionality on top of an already running system.") (native-inputs `(,@(if (and (not (string-prefix? "riscv64" (%current-system))) (string-prefix? "riscv64" arch)) - `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu" #:xgcc gcc-7)) + `(("cross-gcc" ,(cross-gcc "riscv64-linux-gnu")) ("cross-binutils" ,(cross-binutils "riscv64-linux-gnu"))) '()))) (arguments @@ -499,6 +499,11 @@ provide OpenFirmware functionality on top of an already running system.") `("CC=gcc")) "FW_PAYLOAD=n" "V=1") + ;; Direct __asm__ is used with fence.i instructions, which are not + ;; available in the generic riscv ISA. We need a micro-arch with + ;; support for it, and rv64g is the official ISA with support for + ;; fence.i. + #:configure-flags (list "-march=rv64g") #:phases (modify-phases %standard-phases (delete 'configure) -- cgit v1.2.3