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;;; GNU Guix --- Functional package management for GNU
;;; Copyright © 2013 Ludovic Courtès <ludo@gnu.org>
;;;
;;; This file is part of GNU Guix.
;;;
;;; GNU Guix is free software; you can redistribute it and/or modify it
;;; under the terms of the GNU General Public License as published by
;;; the Free Software Foundation; either version 3 of the License, or (at
;;; your option) any later version.
;;;
;;; GNU Guix is distributed in the hope that it will be useful, but
;;; WITHOUT ANY WARRANTY; without even the implied warranty of
;;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;;; GNU General Public License for more details.
;;;
;;; You should have received a copy of the GNU General Public License
;;; along with GNU Guix.  If not, see <http://www.gnu.org/licenses/>.

(define-module (gnu packages cppi)
  #:use-module (guix packages)
  #:use-module (guix download)
  #:use-module (guix build-system gnu)
  #:use-module (guix licenses))

(define-public cppi
  (package
    (name "cppi")
    (version "1.18")
    (source (origin
             (method url-fetch)
             (uri (string-append "mirror://gnu/cppi/cppi-"
                                 version ".tar.xz"))
             (sha256
              (base32
               "1jk42cjaggk71rimjnx3qpmb6hivps0917vl3z7wbxk3i2whb98j"))))
    (build-system gnu-build-system)
    (home-page "https://www.gnu.org/software/cppi/")
    (synopsis "Indent C preprocessor directives to reflect nesting and more")
    (description
     "GNU Cppi processes C source code files to properly indent the
preprocessor directives to reflect their nesting.  It also performs other
standardizations, such as correcting the number of spaces between directives
and the text following them.")
    (license gpl3+)))
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| * | | STALL_O | STALL_O | * |---------------------------------+-----------------------------------------| * | Special requirements | Circuit assumes the use of asynchronous | * | | RAM primitive, e.g. K6R4016V1D. | */ `default_nettype none module sram_slave ( /* Interface to memory */ output wire [17:0] sram_addr, inout wire [15:0] sram_io, output wire sram_cs_n, output wire sram_oe_n, output wire sram_we_n, /* Wishbone slave interface */ output wire ACK_O, input wire [17:0] ADR_I, input wire CLK_I, input wire [15:0] DAT_I, output wire [15:0] DAT_O, input wire RST_I, input wire STB_I, input wire WE_I, output wire STALL_O ); reg writing; reg [15:0] write_data; assign sram_io = sram_we_n ? 16'hZZZZ : write_data; reg sram_cs_not; reg sram_oe_not; reg sram_we_not; assign sram_cs_n = sram_cs_not; assign sram_oe_n = sram_oe_not; assign sram_we_n = sram_we_not; reg [17:0] address; assign sram_addr = address; reg ack; assign ACK_O = ack; reg stall; assign STALL_O = stall; reg [15:0] output_data; assign DAT_O = output_data; reg [2:0] state; always @ (posedge CLK_I) begin output_data <= sram_io; if (RST_I) begin sram_cs_not <= 1; sram_oe_not <= 1; writing <= 0; ack <= 0; stall <= 0; state <= 0; end else begin if (state == 0 || state == 2) begin /* possibly starting new job */ if (STB_I) begin address <= ADR_I; sram_cs_not <= 0; sram_oe_not <= WE_I; writing <= WE_I; write_data <= DAT_I; state <= WE_I ? 1 : 2; stall <= WE_I ? 1 : 0; end else begin // if (STB_I) sram_cs_not <= 1; sram_oe_not <= 1; writing <= 0; state <= 0; end end // if (state == 0 || state == 2) if (state == 1) begin /* performing write; it takes 2 CLK_I cycles */ state <= 2; stall <= 0; end if (state == 2) begin /* finishing job */ ack <= 1; end else begin ack <= 0; end end end // always @ (posedge CLK_I) /* * avoid bus congestion by only driving sram_io * during the middle part of write cycle */ always @ (negedge CLK_I) begin if (writing) sram_we_not <= !sram_we_not; else sram_we_not <= 1; end endmodule // sram_slave
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