From bc43ceac936b48fdccfcac33e172e176273d504f Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Tue, 8 Sep 2020 21:00:13 +0200 Subject: enable slave and master models to use SEL_ signal --- tests/embedded_bram_slave/test.v | 2 ++ tests/intercon/test.v | 13 +++++++++++++ tests/interface_wrapper/test.v | 9 ++++++--- tests/master_arbiter/test.v | 7 +++++++ tests/self/test.v | 5 +++++ tests/self_32bit_word/test.v | 7 +++++++ tests/slave_dispatcher/test.v | 12 ++++++++++++ tests/stack_machine_store/test.v | 19 +++++++++++++++---- tests/wrapped_stack_machine_cond_jump/test.v | 6 ++++++ 9 files changed, 73 insertions(+), 7 deletions(-) (limited to 'tests') diff --git a/tests/embedded_bram_slave/test.v b/tests/embedded_bram_slave/test.v index 94225bd..3671992 100644 --- a/tests/embedded_bram_slave/test.v +++ b/tests/embedded_bram_slave/test.v @@ -23,6 +23,7 @@ module embedded_bram_test(); wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; + wire M_SEL_O; /* Ignored, assumed always high */ wire M_RST_I; wire M_STB_O; wire M_CYC_O; @@ -54,6 +55,7 @@ module embedded_bram_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(M_RST_I), .STB_O(M_STB_O), .CYC_O(M_CYC_O), diff --git a/tests/intercon/test.v b/tests/intercon/test.v index 313f4c6..f2102a6 100644 --- a/tests/intercon/test.v +++ b/tests/intercon/test.v @@ -25,6 +25,7 @@ module intercon_test(); wire [19:0] M0_ADR_O, M1_ADR_O; wire [15:0] M0_DAT_I, M1_DAT_I; wire [15:0] M0_DAT_O, M1_DAT_O; + wire M0_SEL_O, M1_SEL_O; /* Ignored, assumed always high */ wire M0_STB_O, M1_STB_O; wire M0_CYC_O, M1_CYC_O; wire M0_WE_O, M1_WE_O; @@ -35,6 +36,7 @@ module intercon_test(); wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; @@ -58,6 +60,7 @@ module intercon_test(); .ADR_O(M0_ADR_O), .DAT_I(M0_DAT_I), .DAT_O(M0_DAT_O), + .SEL_O(M0_SEL_O), .RST_I(RST), .STB_O(M0_STB_O), .CYC_O(M0_CYC_O), @@ -81,6 +84,7 @@ module intercon_test(); .ADR_O(M1_ADR_O), .DAT_I(M1_DAT_I), .DAT_O(M1_DAT_O), + .SEL_O(M1_SEL_O), .RST_I(RST), .STB_O(M1_STB_O), .CYC_O(M1_CYC_O), @@ -100,6 +104,7 @@ module intercon_test(); .ADR_I(S0_ADR_I), .DAT_I(S0_DAT_I), .DAT_O(S0_DAT_O), + .SEL_I(S0_SEL_I), .RST_I(RST), .STB_I(S0_STB_I), .WE_I(S0_WE_I), @@ -116,6 +121,7 @@ module intercon_test(); .ADR_I(S1_ADR_I), .DAT_I(S1_DAT_I), .DAT_O(S1_DAT_O), + .SEL_I(S1_SEL_I), .RST_I(RST), .STB_I(S1_STB_I), .WE_I(S1_WE_I), @@ -132,6 +138,7 @@ module intercon_test(); .ADR_I(S2_ADR_I), .DAT_I(S2_DAT_I), .DAT_O(S2_DAT_O), + .SEL_I(S2_SEL_I), .RST_I(RST), .STB_I(S2_STB_I), .WE_I(S2_WE_I), @@ -148,6 +155,7 @@ module intercon_test(); .ADR_I(S3_ADR_I), .DAT_I(S3_DAT_I), .DAT_O(S3_DAT_O), + .SEL_I(S3_SEL_I), .RST_I(RST), .STB_I(S3_STB_I), .WE_I(S3_WE_I), @@ -210,6 +218,11 @@ module intercon_test(); .M1_STALL_I(M1_STALL_I) ); + assign S0_SEL_I = 1; + assign S1_SEL_I = 1; + assign S2_SEL_I = 1; + assign S3_SEL_I = 1; + integer i; initial begin diff --git a/tests/interface_wrapper/test.v b/tests/interface_wrapper/test.v index cbd3d88..4031f35 100644 --- a/tests/interface_wrapper/test.v +++ b/tests/interface_wrapper/test.v @@ -22,7 +22,7 @@ module interface_wrapper_test(); wire [20:0] M_RAW_ADR_O; wire [31:0] M_RAW_DAT_I; wire [31:0] M_RAW_DAT_O; - wire [3:0] M_RAW_SEL_O; /* Not used yet, always 4'hF */ + wire [3:0] M_RAW_SEL_O; /* This is being worked on */ wire M_RAW_STB_O; wire M_RAW_CYC_O; wire M_RAW_WE_O; @@ -42,6 +42,7 @@ module interface_wrapper_test(); wire [19:0] S_ADR_I; wire [15:0] S_DAT_I; wire [15:0] S_DAT_O; + wire S_SEL_I; /* Always high */ wire S_RST_I; wire S_STB_I; wire S_WE_I; @@ -54,6 +55,7 @@ module interface_wrapper_test(); #( .MASTER_NR(0), .WORD_SIZE(4), + .SEL_LINES(4), .ADR_BITS(21), .OPERATIONS_FILE("operations.mem"), .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) @@ -64,6 +66,7 @@ module interface_wrapper_test(); .ADR_O(M_RAW_ADR_O), .DAT_I(M_RAW_DAT_I), .DAT_O(M_RAW_DAT_O), + .SEL_O(M_RAW_SEL_O), .RST_I(M_RST_I), .STB_O(M_RAW_STB_O), .CYC_O(M_RAW_CYC_O), @@ -85,6 +88,7 @@ module interface_wrapper_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(S_RST_I), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -127,11 +131,10 @@ interface_wrapper wrapper assign M_WRAPPED_DAT_I = S_DAT_O; assign M_WRAPPED_STALL_I = S_STALL_O; - assign M_RAW_SEL_O = 4'hF; - assign S_CLK_I = CLK; assign S_ADR_I = M_WRAPPED_ADR_O; assign S_DAT_I = M_WRAPPED_DAT_O; + assign S_SEL_I = 1; assign S_RST_I = RST; assign S_STB_I = M_WRAPPED_STB_O && M_WRAPPED_CYC_O; assign S_WE_I = M_WRAPPED_WE_O; diff --git a/tests/master_arbiter/test.v b/tests/master_arbiter/test.v index bcf90b8..58e3add 100644 --- a/tests/master_arbiter/test.v +++ b/tests/master_arbiter/test.v @@ -22,6 +22,7 @@ module master_arbiter_test(); wire [19:0] M0_ADR_O; wire [15:0] M0_DAT_I; wire [15:0] M0_DAT_O; + wire M0_SEL_O; /* Ignored, assumed always high */ wire M0_STB_O; wire M0_CYC_O; wire M0_WE_O; @@ -31,6 +32,7 @@ module master_arbiter_test(); wire [19:0] M1_ADR_O; wire [15:0] M1_DAT_I; wire [15:0] M1_DAT_O; + wire M1_SEL_O; /* Ignored, assumed always high */ wire M1_STB_O; wire M1_CYC_O; wire M1_WE_O; @@ -40,6 +42,7 @@ module master_arbiter_test(); wire [19:0] S_ADR_I; wire [15:0] S_DAT_I; wire [15:0] S_DAT_O; + wire S_SEL_I; /* Always high */ wire S_STB_I; wire S_WE_I; wire S_STALL_O; @@ -76,6 +79,7 @@ module master_arbiter_test(); .ADR_O(M0_ADR_O), .DAT_I(M0_DAT_I), .DAT_O(M0_DAT_O), + .SEL_O(M0_SEL_O), .RST_I(RST), .STB_O(M0_STB_O), .CYC_O(M0_CYC_O), @@ -99,6 +103,7 @@ module master_arbiter_test(); .ADR_O(M1_ADR_O), .DAT_I(M1_DAT_I), .DAT_O(M1_DAT_O), + .SEL_O(M1_SEL_O), .RST_I(RST), .STB_O(M1_STB_O), .CYC_O(M1_CYC_O), @@ -120,6 +125,7 @@ module master_arbiter_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(RST), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -165,6 +171,7 @@ module master_arbiter_test(); assign S_ADR_I = M_COMBINED_ADR_O[19:0]; assign S_DAT_I = M_COMBINED_DAT_O; + assign S_SEL_I = 1; assign S_STB_I = M_COMBINED_STB_O && M_COMBINED_CYC_O; assign S_WE_I = M_COMBINED_WE_O; diff --git a/tests/self/test.v b/tests/self/test.v index 8eb0617..323dba2 100644 --- a/tests/self/test.v +++ b/tests/self/test.v @@ -18,6 +18,7 @@ module self_test(); wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; + wire M_SEL_O; /* Always high in this test */ wire M_RST_I; wire M_STB_O; wire M_CYC_O; @@ -29,6 +30,7 @@ module self_test(); wire [17:0] S_ADR_I; wire [15:0] S_DAT_I; wire [15:0] S_DAT_O; + wire S_SEL_I; /* Always high in this test */ wire S_RST_I; wire S_STB_I; wire S_WE_I; @@ -49,6 +51,7 @@ module self_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(M_RST_I), .STB_O(M_STB_O), .CYC_O(M_CYC_O), @@ -68,6 +71,7 @@ module self_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(S_RST_I), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -86,6 +90,7 @@ module self_test(); assign S_CLK_I = CLK; assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */ assign S_DAT_I = M_DAT_O; + assign S_SEL_I = M_SEL_O; assign S_RST_I = RST; assign S_STB_I = M_STB_O && M_CYC_O; assign S_WE_I = M_WE_O; diff --git a/tests/self_32bit_word/test.v b/tests/self_32bit_word/test.v index 804b4d3..871fe0c 100644 --- a/tests/self_32bit_word/test.v +++ b/tests/self_32bit_word/test.v @@ -19,6 +19,7 @@ module self_32bit_test(); wire [21:0] M_ADR_O; wire [31:0] M_DAT_I; wire [31:0] M_DAT_O; + wire [3:0] M_SEL_O; wire M_RST_I; wire M_STB_O; wire M_CYC_O; @@ -30,6 +31,7 @@ module self_32bit_test(); wire [21:0] S_ADR_I; wire [31:0] S_DAT_I; wire [31:0] S_DAT_O; + wire [3:0] S_SEL_I; wire S_RST_I; wire S_STB_I; wire S_WE_I; @@ -42,6 +44,7 @@ module self_32bit_test(); #( .MASTER_NR(0), .WORD_SIZE(4), + .SEL_LINES(4), .ADR_BITS(22), .OPERATIONS_FILE("operations.mem"), .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) @@ -52,6 +55,7 @@ module self_32bit_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(M_RST_I), .STB_O(M_STB_O), .CYC_O(M_CYC_O), @@ -65,6 +69,7 @@ module self_32bit_test(); #( .SLAVE_NR(0), .WORD_SIZE(4), + .SEL_LINES(4), .ADR_BITS(22) ) slave ( @@ -73,6 +78,7 @@ module self_32bit_test(); .ADR_I(S_ADR_I), .DAT_I(S_DAT_I), .DAT_O(S_DAT_O), + .SEL_I(S_SEL_I), .RST_I(S_RST_I), .STB_I(S_STB_I), .WE_I(S_WE_I), @@ -91,6 +97,7 @@ module self_32bit_test(); assign S_CLK_I = CLK; assign S_ADR_I = M_ADR_O; assign S_DAT_I = M_DAT_O; + assign S_SEL_I = M_SEL_O; assign S_RST_I = RST; assign S_STB_I = M_STB_O && M_CYC_O; assign S_WE_I = M_WE_O; diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v index d29b05c..49c03ef 100644 --- a/tests/slave_dispatcher/test.v +++ b/tests/slave_dispatcher/test.v @@ -20,6 +20,7 @@ module slave_dispatcher_test(); wire [19:0] M_ADR_O; wire [15:0] M_DAT_I; wire [15:0] M_DAT_O; + wire M_SEL_O; /* Ignored, assumed always high */ wire M_STB_O; wire M_CYC_O; wire M_WE_O; @@ -30,6 +31,7 @@ module slave_dispatcher_test(); wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; @@ -57,6 +59,7 @@ module slave_dispatcher_test(); .ADR_O(M_ADR_O), .DAT_I(M_DAT_I), .DAT_O(M_DAT_O), + .SEL_O(M_SEL_O), .RST_I(RST), .STB_O(M_STB_O), .CYC_O(M_CYC_O), @@ -76,6 +79,7 @@ module slave_dispatcher_test(); .ADR_I(S0_ADR_I), .DAT_I(S0_DAT_I), .DAT_O(S0_DAT_O), + .SEL_I(S0_SEL_I), .RST_I(RST), .STB_I(S0_STB_I), .WE_I(S0_WE_I), @@ -92,6 +96,7 @@ module slave_dispatcher_test(); .ADR_I(S1_ADR_I), .DAT_I(S1_DAT_I), .DAT_O(S1_DAT_O), + .SEL_I(S1_SEL_I), .RST_I(RST), .STB_I(S1_STB_I), .WE_I(S1_WE_I), @@ -108,6 +113,7 @@ module slave_dispatcher_test(); .ADR_I(S2_ADR_I), .DAT_I(S2_DAT_I), .DAT_O(S2_DAT_O), + .SEL_I(S2_SEL_I), .RST_I(RST), .STB_I(S2_STB_I), .WE_I(S2_WE_I), @@ -124,6 +130,7 @@ module slave_dispatcher_test(); .ADR_I(S3_ADR_I), .DAT_I(S3_DAT_I), .DAT_O(S3_DAT_O), + .SEL_I(S3_SEL_I), .RST_I(RST), .STB_I(S3_STB_I), .WE_I(S3_WE_I), @@ -185,6 +192,11 @@ module slave_dispatcher_test(); assign S_COMBINED_STB_I = M_STB_O && M_CYC_O; assign S_COMBINED_WE_I = M_WE_O; + assign S0_SEL_I = 1; + assign S1_SEL_I = 1; + assign S2_SEL_I = 1; + assign S3_SEL_I = 1; + integer i; initial begin diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v index 08230a3..98ea2dc 100644 --- a/tests/stack_machine_store/test.v +++ b/tests/stack_machine_store/test.v @@ -36,7 +36,7 @@ module stack_machine_test(); wire [20:0] MD_ADR_O; wire [31:0] MD_DAT_I; wire [31:0] MD_DAT_O; - wire [3:0] MD_SEL_O; /* Ignored for now */ + wire [3:0] MD_SEL_O; wire MD_STB_O; wire MD_CYC_O; wire MD_WE_O; @@ -48,6 +48,7 @@ module stack_machine_test(); wire [19:0] SI_ADR_I; wire [15:0] SI_DAT_I; wire [15:0] SI_DAT_O; + wire SI_SEL_I; wire SI_RST_I; wire SI_STB_I; wire SI_WE_I; @@ -58,6 +59,7 @@ module stack_machine_test(); wire [20:0] SD_ADR_I; wire [31:0] SD_DAT_I; wire [31:0] SD_DAT_O; + wire [3:0] SD_SEL_I; wire SD_RST_I; wire SD_STB_I; wire SD_WE_I; @@ -111,6 +113,7 @@ module stack_machine_test(); .ADR_I(SI_ADR_I), .DAT_I(SI_DAT_I), .DAT_O(SI_DAT_O), + .SEL_I(SI_SEL_I), .RST_I(SI_RST_I), .STB_I(SI_STB_I), .WE_I(SI_WE_I), @@ -121,6 +124,7 @@ module stack_machine_test(); #( .SLAVE_NR(1), .WORD_SIZE(4), + .SEL_LINES(4), .ADR_BITS(21), .WRITABLE(1), .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT), @@ -132,6 +136,7 @@ module stack_machine_test(); .ADR_I(SD_ADR_I), .DAT_I(SD_DAT_I), .DAT_O(SD_DAT_O), + .SEL_I(SD_SEL_I), .RST_I(SD_RST_I), .STB_I(SD_STB_I), .WE_I(SD_WE_I), @@ -155,6 +160,7 @@ module stack_machine_test(); assign SI_CLK_I = CLK; assign SI_ADR_I = MI_ADR_O; assign SI_DAT_I = MI_DAT_O; + assign SI_SEL_I = 1; assign SI_RST_I = RST; assign SI_STB_I = MI_STB_O && MI_CYC_O; assign SI_WE_I = MI_WE_O; @@ -162,6 +168,7 @@ module stack_machine_test(); assign SD_CLK_I = CLK; assign SD_ADR_I = MD_ADR_O; assign SD_DAT_I = MD_DAT_O; + assign SD_SEL_I = MD_SEL_O; assign SD_RST_I = RST; assign SD_STB_I = MD_STB_O && MD_CYC_O; assign SD_WE_I = MD_WE_O; @@ -169,6 +176,7 @@ module stack_machine_test(); integer i, j; reg [21:0] address; reg [31:0] expected_value; + reg [31:0] found_value; reg [31:0] words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0]; @@ -189,12 +197,15 @@ module stack_machine_test(); 0, `WORDS_TO_VERIFY_COUNT * 2 - 1); for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin - /* Keep in mind we haven't implemented byte-grained access yet */ address = words_to_verify[2 * j][21:0]; + found_value = {slave_D.memory[address + 3], + slave_D.memory[address + 2], + slave_D.memory[address + 1], + slave_D.memory[address]}; expected_value = words_to_verify[2 * j + 1]; - if (slave_D.memory[address] !== expected_value) begin + if (found_value !== expected_value) begin `MSG(("error: expected h%x at h%x, but got h%x", - expected_value, address, slave_D.memory[address])); + expected_value, address, found_value)); end end diff --git a/tests/wrapped_stack_machine_cond_jump/test.v b/tests/wrapped_stack_machine_cond_jump/test.v index 4dff60c..7845045 100644 --- a/tests/wrapped_stack_machine_cond_jump/test.v +++ b/tests/wrapped_stack_machine_cond_jump/test.v @@ -44,6 +44,7 @@ module wrapped_stack_machine_test(); wire [19:0] SI_ADR_I; wire [15:0] SI_DAT_I; wire [15:0] SI_DAT_O; + wire SI_SEL_I; wire SI_STB_I; wire SI_WE_I; wire SI_STALL_O; @@ -52,6 +53,7 @@ module wrapped_stack_machine_test(); wire [19:0] SD_ADR_I; wire [15:0] SD_DAT_I; wire [15:0] SD_DAT_O; + wire SD_SEL_I; wire SD_STB_I; wire SD_WE_I; wire SD_STALL_O; @@ -102,6 +104,7 @@ module wrapped_stack_machine_test(); .ADR_I(SI_ADR_I), .DAT_I(SI_DAT_I), .DAT_O(SI_DAT_O), + .SEL_I(SI_SEL_I), .RST_I(RST), .STB_I(SI_STB_I), .WE_I(SI_WE_I), @@ -121,6 +124,7 @@ module wrapped_stack_machine_test(); .ADR_I(SD_ADR_I), .DAT_I(SD_DAT_I), .DAT_O(SD_DAT_O), + .SEL_I(SD_SEL_I), .RST_I(RST), .STB_I(SD_STB_I), .WE_I(SD_WE_I), @@ -137,11 +141,13 @@ module wrapped_stack_machine_test(); assign SI_ADR_I = MI_ADR_O; assign SI_DAT_I = MI_DAT_O; + assign SI_SEL_I = 1; assign SI_STB_I = MI_STB_O && MI_CYC_O; assign SI_WE_I = MI_WE_O; assign SD_ADR_I = MD_ADR_O; assign SD_DAT_I = MD_DAT_O; + assign SD_SEL_I = 1; assign SD_STB_I = MD_STB_O && MD_CYC_O; assign SD_WE_I = MD_WE_O; -- cgit v1.2.3