From 31e0d5f3a684b2e33f7b74e86b2ab6d30c4d2aba Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Sat, 21 Nov 2020 18:38:36 +0100 Subject: increase number of wb slaves, that can be attached to the intercon --- tests/intercon/test.v | 90 +++++++++++++++++++++++++++++----- tests/slave_dispatcher/operations.memv | 28 +++++++---- tests/slave_dispatcher/test.v | 90 +++++++++++++++++++++++++++++----- 3 files changed, 174 insertions(+), 34 deletions(-) (limited to 'tests') diff --git a/tests/intercon/test.v b/tests/intercon/test.v index f2102a6..721502c 100644 --- a/tests/intercon/test.v +++ b/tests/intercon/test.v @@ -31,16 +31,26 @@ module intercon_test(); wire M0_WE_O, M1_WE_O; wire M0_STALL_I, M1_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, + S3_CLK_I, S4_CLK_I, S5_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, + S3_SEL_I, S4_SEL_I, S5_SEL_I; /* Always high */ + wire S0_RST_I, S1_RST_I, S2_RST_I, + S3_RST_I, S4_RST_I, S5_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; /* Non-wishbone */ wire M0_finished; @@ -130,7 +140,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(2) + .SLAVE_NR(2), + .ADR_BITS(17) ) slave2 ( .ACK_O(S2_ACK_O), @@ -147,7 +158,8 @@ module intercon_test(); memory_slave_model #( - .SLAVE_NR(3) + .SLAVE_NR(3), + .ADR_BITS(17) ) slave3 ( .ACK_O(S3_ACK_O), @@ -162,6 +174,42 @@ module intercon_test(); .STALL_O(S3_STALL_O) ); + memory_slave_model + #( + .SLAVE_NR(4), + .ADR_BITS(17) + ) slave4 + ( + .ACK_O(S4_ACK_O), + .CLK_I(CLK), + .ADR_I(S4_ADR_I), + .DAT_I(S4_DAT_I), + .DAT_O(S4_DAT_O), + .SEL_I(S4_SEL_I), + .RST_I(RST), + .STB_I(S4_STB_I), + .WE_I(S4_WE_I), + .STALL_O(S4_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(5), + .ADR_BITS(17) + ) slave5 + ( + .ACK_O(S5_ACK_O), + .CLK_I(CLK), + .ADR_I(S5_ADR_I), + .DAT_I(S5_DAT_I), + .DAT_O(S5_DAT_O), + .SEL_I(S5_SEL_I), + .RST_I(RST), + .STB_I(S5_STB_I), + .WE_I(S5_WE_I), + .STALL_O(S5_STALL_O) + ); + intercon intercon ( .CLK(CLK), @@ -199,6 +247,22 @@ module intercon_test(); .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .M0_ACK_I(M0_ACK_I), .M0_ADR_O(M0_ADR_O), .M0_DAT_I(M0_DAT_I), @@ -222,6 +286,8 @@ module intercon_test(); assign S1_SEL_I = 1; assign S2_SEL_I = 1; assign S3_SEL_I = 1; + assign S4_SEL_I = 1; + assign S5_SEL_I = 1; integer i; diff --git a/tests/slave_dispatcher/operations.memv b/tests/slave_dispatcher/operations.memv index 8785d5c..ab534f6 100644 --- a/tests/slave_dispatcher/operations.memv +++ b/tests/slave_dispatcher/operations.memv @@ -1,6 +1,6 @@ `include "macroasm.vh" // look into macroasm.vh for more info -// The beginning copied from self test, only 1st slave is being accessed. +// The beginning copied from self test, only slave 0 is being accessed. `WRITE(00000, abcd) `WAIT `READ (00000, abcd) @@ -29,35 +29,43 @@ `WRITE(40040, efef) `WRITE(80002, 1f1f) `WRITE(c00c0, 1d1d) +`WRITE(a0002, aaea) +`WRITE(e00c0, cc4d) `READ (80002, 1f1f) `READ (c00c0, 1d1d) `READ (40040, efef) +`READ (a0002, aaea) +`READ (e00c0, cc4d) `WAIT `WAIT -// Make a sequence of commands to slave 3 (addresses c0000 - fffff) +// Make a sequence of commands to slave 4 (addresses c0000 - dffff) `READ (c00c0, 1d1d) `WRITE(c1111, 0022) `READ (c00c0, 1d1d) +`WRITE(c00c0, 0111) `WRITE(c0001, 0001) `WRITE(c0002, 0002) `READ (c0001, 0001) `READ (c0002, 0002) `READ (c0001, 0001) +`READ (c00c0, 0111) `WRITE(c0003, 0003) `WRITE(c0002, 2222) `READ (c0002, 2222) `READ (c0003, 0003) -`WRITE(fffff, 5555) +`WRITE(dffff, 5555) `READ (c1111, 0022) -// Put a single command to another slave in-between commands to slave 3 +// Put a single command to another slave in-between commands to slave 4 `WRITE(4ffff, b6b6) -`READ (fffff, 5555) -`WRITE(eeeee, aaaa) -`READ (eeeee, aaaa) -// Let slave 3 take a breath now +`READ (dffff, 5555) +`WRITE(deeee, aaaa) +`READ (deeee, aaaa) +// Let slave 4 take a breath now `READ (4ffff, b6b6) `DESELECT -// We made writes to c0002 and c0001, make sure corresponding addreses -// in other slaves were not overwritten by mistake +// We made writes to c0002, c0001 and c00c0, make sure corresponding +// addreses in other slaves were not overwritten by mistake `READ (80002, 1f1f) +`READ (a0002, aaea) `READ (00001, 4321) +`READ (e00c0, cc4d) diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v index 49c03ef..ad85b1f 100644 --- a/tests/slave_dispatcher/test.v +++ b/tests/slave_dispatcher/test.v @@ -26,16 +26,26 @@ module slave_dispatcher_test(); wire M_WE_O; wire M_STALL_I; - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_SEL_I, S1_SEL_I, S2_SEL_I, S3_SEL_I; /* Always high */ - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, + S3_ACK_O, S4_ACK_O, S5_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, + S3_CLK_I, S4_CLK_I, S5_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I; + wire [16:0] S2_ADR_I, S3_ADR_I, S4_ADR_I, S5_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, + S3_DAT_I, S4_DAT_I, S5_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, + S3_DAT_O, S4_DAT_O, S5_DAT_O; + wire S0_SEL_I, S1_SEL_I, S2_SEL_I, + S3_SEL_I, S4_SEL_I, S5_SEL_I; /* Always high */ + wire S0_RST_I, S1_RST_I, S2_RST_I, + S3_RST_I, S4_RST_I, S5_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, + S3_STB_I, S4_STB_I, S5_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, + S3_WE_I, S4_WE_I, S5_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, + S3_STALL_O, S4_STALL_O, S5_STALL_O; wire S_COMBINED_ACK_O; wire [19:0] S_COMBINED_ADR_I; @@ -105,7 +115,8 @@ module slave_dispatcher_test(); memory_slave_model #( - .SLAVE_NR(2) + .SLAVE_NR(2), + .ADR_BITS(17) ) slave2 ( .ACK_O(S2_ACK_O), @@ -122,7 +133,8 @@ module slave_dispatcher_test(); memory_slave_model #( - .SLAVE_NR(3) + .SLAVE_NR(3), + .ADR_BITS(17) ) slave3 ( .ACK_O(S3_ACK_O), @@ -137,6 +149,42 @@ module slave_dispatcher_test(); .STALL_O(S3_STALL_O) ); + memory_slave_model + #( + .SLAVE_NR(4), + .ADR_BITS(17) + ) slave4 + ( + .ACK_O(S4_ACK_O), + .CLK_I(CLK), + .ADR_I(S4_ADR_I), + .DAT_I(S4_DAT_I), + .DAT_O(S4_DAT_O), + .SEL_I(S4_SEL_I), + .RST_I(RST), + .STB_I(S4_STB_I), + .WE_I(S4_WE_I), + .STALL_O(S4_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(3), + .ADR_BITS(17) + ) slave5 + ( + .ACK_O(S5_ACK_O), + .CLK_I(CLK), + .ADR_I(S5_ADR_I), + .DAT_I(S5_DAT_I), + .DAT_O(S5_DAT_O), + .SEL_I(S5_SEL_I), + .RST_I(RST), + .STB_I(S5_STB_I), + .WE_I(S5_WE_I), + .STALL_O(S5_STALL_O) + ); + slave_dispatcher dispatcher ( .CLK(CLK), @@ -174,6 +222,22 @@ module slave_dispatcher_test(); .S3_WE_I(S3_WE_I), .S3_STALL_O(S3_STALL_O), + .S4_ACK_O(S4_ACK_O), + .S4_ADR_I(S4_ADR_I), + .S4_DAT_I(S4_DAT_I), + .S4_DAT_O(S4_DAT_O), + .S4_STB_I(S4_STB_I), + .S4_WE_I(S4_WE_I), + .S4_STALL_O(S4_STALL_O), + + .S5_ACK_O(S5_ACK_O), + .S5_ADR_I(S5_ADR_I), + .S5_DAT_I(S5_DAT_I), + .S5_DAT_O(S5_DAT_O), + .S5_STB_I(S5_STB_I), + .S5_WE_I(S5_WE_I), + .S5_STALL_O(S5_STALL_O), + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), .S_COMBINED_ADR_I(S_COMBINED_ADR_I), .S_COMBINED_DAT_I(S_COMBINED_DAT_I), @@ -196,6 +260,8 @@ module slave_dispatcher_test(); assign S1_SEL_I = 1; assign S2_SEL_I = 1; assign S3_SEL_I = 1; + assign S4_SEL_I = 1; + assign S5_SEL_I = 1; integer i; -- cgit v1.2.3