From dc2da16edf07a928308dab7d7f998ef00784dc7a Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Thu, 16 Jul 2020 17:04:12 +0200 Subject: use separate registers for information whether displaying of a vga pixel/row starts on next tick (optimization to make combinational logic delay shorter) --- src/example.v | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'src/example.v') diff --git a/src/example.v b/src/example.v index c83bea2..0609d69 100644 --- a/src/example.v +++ b/src/example.v @@ -320,8 +320,8 @@ module vga_timing(input wire clock_50mhz, output reg h_sync, output reg v_sync, output reg display_on, - output wire pixel_starting, - output wire row_starting); + output reg pixel_starting, + output reg row_starting); parameter h_pixels = 640; parameter v_pixels = 480; @@ -364,12 +364,16 @@ module vga_timing(input wire clock_50mhz, h_sync <= ~h_pol; v_sync <= ~v_pol; display_on <= 0; + pixel_starting <= 0; + row_starting <= 0; end // if (reset) else begin divider <= divider + 1; if (divider == 1'b1) begin display_on <= display_on_next_tick; + pixel_starting <= display_on_next_tick; + row_starting <= display_on_next_tick && h_counter == h_active_video_start - 1; if (h_counter < h_frame_end - 1) begin h_counter <= h_counter + 1; @@ -389,11 +393,12 @@ module vga_timing(input wire clock_50mhz, end // else: !if(v_counter < v_frame_end - 1) end // else: !if(h_counter < h_frame_end - 1) end // if (divider == 1'b1) + else begin + pixel_starting <= 0; + row_starting <= 0; + end end // else: !if(reset) end // always @ (posedge clock_50mhz) - - assign pixel_starting = display_on && divider == 1'b0; - assign row_starting = pixel_starting && h_counter == h_active_video_start; endmodule // vga_timing module vga_pass_colors(input wire clock_50mhz, -- cgit v1.2.3