From 96e4965c09bd41f11162120d6312f2aae7efe7ea Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Thu, 31 Dec 2020 17:59:37 +0100 Subject: Add Wishbone datasheets --- design/spi_slave.v | 87 +++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) (limited to 'design/spi_slave.v') diff --git a/design/spi_slave.v b/design/spi_slave.v index a53d9d2..5c671aa 100644 --- a/design/spi_slave.v +++ b/design/spi_slave.v @@ -1,3 +1,87 @@ +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | SPI master core | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | $clog2(MEMORY_BLOCKS + 1) + 8 bits | + * |---------------------------------+-----------------------------------------| + * | | NONE (determined by SPI slave devices | + * | Clock frequency constraints | and connections to them and also by | + * | | memory primitive inferred) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | | Circuit assumes the use of synchronous | + * | Special requirements | RAM with asynchronour read | + * | | inreffable by synthesis software. | + * |---------------------------------+-----------------------------------------| + * | | The MEMORY_BLOCKS parameter can be used | + * | | to decide the size of module's data | + * | | transfer memory. SPI operations are | + * | | performed as follows: | + * | Additional information | * Bytes to send through MOSI are | + * | | written at the beginning of data | + * | | transfer memory. | + * | | * Number of bytes to send is | + * | | written to the "bytes_to_output" | + * | | register. | + * | | * Number of bytes to receive from | + * | | MISO afterwards is written to the | + * | | "bytes_to_recive" register. | + * | | * Operation is started by writing | + * | | any value to the "operating" | + * | | register. | + * | | Also see the memory map below. | + * | | The "operating" register can be | + * | | read at any time to check if an | + * | | SPI operation has finished. It | + * | | reads a non-zero value if and only | + * | | if the SPI operation is still | + * | | occuring. Register writes are not | + * | | possible during SPI operation. Any | + * | | such write will be stalled and will | + * | | complete after SPI operation | + * | | finishes. This behavior can be | + * | | exploited to wait for operation | + * | | completion. | + */ + +/* + * The memory map is as follows: + * h000 - (h100*MEMORY_BLOCKS)-1 - data transfer memory + * h100*MEMORY_BLOCKS - "bytes_to_output" reg + * (h100*MEMORY_BLOCKS)+1 - "bytes_to_receive" reg + * (h100*MEMORY_BLOCKS)+2 - (h100*MEMORY_BLOCKS)+3 - "operating" reg + * + * If MEMORY_BLOCKS is set to 1, this results in the following memory map: + * h000 - h0FF - data transfer memory + * h100 - "bytes_to_output" reg + * h101 - "bytes_to_receive" reg + * h102 - h103 - "operating" reg + * + * Accessing any half of the "operating" reg results in the same behavior. + * Accessing higher addresses than specified results in UNDEFINED behavior. + */ + `default_nettype none `define ADDR_WIDTH ($clog2(MEMORY_BLOCKS + 1) + 8) @@ -102,7 +186,8 @@ module spi_slave wire wb_mwrite_completes; wire wb_rwrite_completes; - assign wb_mread_completes = !(spi_read_memory[0] || initial_spi_read_memory) && + assign wb_mread_completes = !(spi_read_memory[0] || + initial_spi_read_memory) && wb_read_memory[0]; assign wb_rread_completes = wb_read_regs; /* can always read immediately */ -- cgit v1.2.3