From 3cdcd0cbaf54520b8e9111048b8729cc973ded28 Mon Sep 17 00:00:00 2001
From: Wojciech Kosior <kwojtus@protonmail.com>
Date: Wed, 1 Apr 2020 11:49:22 +0200
Subject: add simple readme

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 README.txt | 2 ++
 1 file changed, 2 insertions(+)
 create mode 100644 README.txt

(limited to 'README.txt')

diff --git a/README.txt b/README.txt
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+This repository shall contain the the code for 'Laboratory station based on programmable logic device for WebAssembly execution evaluation' developed as my engineering thesis at AGH University of Science and Technology in Cracov, Poland.
+The project is going to utilize the Verilog HDL. Icarus Verilog Simulator shall be used for simulation and test benches, while Yosys, arachne-pnr/nextpnr and icestorm are the tools chosen for synthesis, p&r and bitstream generation for Olimex's iCE40HX8K-EVB FPGA.
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