From f122fa70e30a7d7744b38fa22bd1d5aa949e8277 Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Thu, 24 Dec 2020 09:22:34 +0100 Subject: prepare makefile infrastructure for writing examples --- Makefile | 64 +++++------ Makefile.config | 1 + Makefile.example | 39 +++++++ Makefile.test | 31 ++---- Makefile.util | 62 ++++++++++- design/soc.v | 20 +++- examples/example1_blink_led/Makefile | 3 + examples/example1_blink_led/instructions.s.tcl | 57 ++++++++++ examples/example_toplevel.v | 142 +++++++++++++++++++++++++ models/flash_memory.v | 9 +- models/soc_with_peripherals.v | 7 +- tests/soc_measure_time/test.v | 6 ++ tests/soc_print_number/test.v | 6 ++ tests/soc_simple_display/test.v | 6 ++ 14 files changed, 391 insertions(+), 62 deletions(-) create mode 100644 Makefile.example create mode 100644 examples/example1_blink_led/Makefile create mode 100644 examples/example1_blink_led/instructions.s.tcl create mode 100644 examples/example_toplevel.v diff --git a/Makefile b/Makefile index 39f1f1b..cad5c5f 100644 --- a/Makefile +++ b/Makefile @@ -1,40 +1,34 @@ -PROJ_DIR := . +PROJ_DIR := ./ + +def : design.bin -include Makefile.config include Makefile.util -include tools/Makefile.tools -TEST_TARGETS := $(addprefix test_,$(shell ls tests)) +IVFLAGS += -Iinclude/ -TOOLS_TARGETS := $(addprefix tools/,$(TOOLS)) +TESTS := $(notdir \ + $(shell find $(PROJ_DIR)/tests -maxdepth 1 -mindepth 1 -type d)) -GENERATED_MEM_FILES := $(shell find design/ -name "*.s.tcl") -GENERATED_MEM_FILES := $(basename $(basename $(GENERATED_MEM_FILES))) -GENERATED_MEM_FILES := $(addsuffix .mem,$(GENERATED_MEM_FILES)) +TEST_TARGETS := $(addprefix test_,$(TESTS)) -all : design.bin +EXAMPLES := $(notdir \ + $(shell find $(PROJ_DIR)/examples -maxdepth 1 -mindepth 1 -type d)) +EXAMPLE_SIM_TARGETS := $(addprefix simulate_,$(EXAMPLES)) +EXAMPLE_BUILD_TARGETS := $(addprefix build_,$(EXAMPLES)) +EXAMPLE_PROG_TARGETS := $(addprefix prog_,$(EXAMPLES)) -design.v : design/rom.mem design/*.v - $(IV) -Iinclude/ -E $(filter %.v,$^) \ +design.v : design/rom.mem design/*.v design/font.mem + $(IV) $(IVFLAGS) -E $(filter %.v,$^) \ -DROM_WORDS_COUNT=$(call FILE_LINES,$<) -o $@ -design.json : design.v design/rom.mem design/font.mem - $(YOSYS) -p 'read_verilog -defer $<' \ - -p 'synth_ice40 -top $(TOPMODULE) -json $@' - -design.asc : design.json $(PCF) - $(PNR) --hx8k --asc $@ --pcf $(PCF) --json $< --package ct256 - -design.bin : design.asc - $(ICEPACK) $< $@ +# Yosys synthesis (generates design.json), NextPNR routing (generates +# design.asc), bitstream generation (generates design.bin) and programming +# were moved to Makefile.util, so that they can be reused in examples. timing.rpt : design.asc $(ICETIME) -d hx8k -mtr $@ $< -prog : design.bin - sudo iceprogduino $< - CALL_TESTS = \ cd tests/; \ @@ -65,18 +59,26 @@ wasm_compile_test : $(TEST_TARGETS) : test_% : $(MAKE) -C tests/$* +$(EXAMPLE_SIM_TARGETS) : simulate_% : + $(MAKE) -C examples/$* -tools : $(TOOLS_TARGETS) +$(EXAMPLE_BUILD_TARGETS) : build_% : + $(MAKE) -C examples/$* design.bin + +$(EXAMPLE_PROG_TARGETS) : prog_% : + $(MAKE) -C examples/$* prog -$(TOOLS_TARGETS) : tools/% : - $(MAKE) -C tools/ $* +tools : $(TOOLS_TARGETS) clean : - for TEST in tests/*; do $(MAKE) -C $$TEST clean >/dev/null; done - rm $(GENERATED_MEM_FILES) 2>/dev/null || true + for TEST in tests/*/; do $(MAKE) -C $$TEST clean >/dev/null; done + for EXAMP in examples/*/; do $(MAKE) -C $$EXAMP clean > /dev/null; done + rm $(call FIND_GENERATED_FILES,design/) 2>/dev/null || true $(MAKE) -C tools/ clean >/dev/null - rm $(addprefix design.,v json asc bin) timing.rpt 2>/dev/null || true + rm $(addprefix design.,v json asc bin) timing.rpt \ + $(addsuffix .log,yosys pnr) 2>/dev/null || true -.PHONY : all tools test quicktest stack_machine_test stack_machine_quicktest \ - wasm_compile_test $(TEST_TARGETS) $(TOOLS_TARGETS) tools +.PHONY : def tools test quicktest stack_machine_test stack_machine_quicktest \ + wasm_compile_test $(TEST_TARGETS) $(TOOLS_TARGETS) tools \ + $(EXAMPLE_SIM_TARGETS) $(EXAMPLE_BUILD_TARGETS) $(EXAMPLE_PROG_TARGETS) diff --git a/Makefile.config b/Makefile.config index a67e9f1..d0299e8 100644 --- a/Makefile.config +++ b/Makefile.config @@ -11,6 +11,7 @@ CFLAGS += -O2 endif IV = iverilog +VVP = vvp YOSYS = git-yosys PNR = git-nextpnr-ice40 diff --git a/Makefile.example b/Makefile.example new file mode 100644 index 0000000..e44cf9c --- /dev/null +++ b/Makefile.example @@ -0,0 +1,39 @@ +# This Makefile is to be included by Makefile of each example + +ifndef PROJ_DIR +PROJ_DIR := ../../ +endif + +def : simulate + +include $(PROJ_DIR)/Makefile.util + +DESIGN_DIR := $(PROJ_DIR)/design/ +FONT := $(DESIGN_DIR)/font.mem + +IVFLAGS += -I$(PROJ_DIR)/include/ + +ROM_DEFINES = \ + -DROM_WORDS_COUNT=$(call FILE_LINES,instructions.mem) \ + -DEMBEDDED_ROM_FILE=\"instructions.mem\" \ + -DFONT_FILE=\"$(FONT)\" + +example.vvp : $(DESIGN_DIR)/*.v soc_with_peripherals.v flash_memory.v sram.v \ + vga_display.v example_toplevel.v $(FONT) messages.vh \ + instructions.mem + $(IV) $(IVFLAGS) $(SIMFLAGS) -DSIMULATION $(ROM_DEFINES) \ + -s example $(filter %.v,$^) -o $@ + +simulate : example.vvp + $(VVP) $< + +design.v : instructions.mem $(DESIGN_DIR)/*.v $(FONT) + $(IV) $(IVFLAGS) $(ROM_DEFINES) -E $(filter %.v,$^) -o $@ + +clean : + find . -name "*.vvp" -delete + rm $(call FIND_GENERATED_FILES,.) $(addprefix design.,v json asc bin) \ + $(addsuffix .log,yosys pnr) VGAdump.mem VGAdump.ppm \ + 2>/dev/null || true + +.PHONY : def simulate clean diff --git a/Makefile.test b/Makefile.test index 8572811..d6ac8ab 100644 --- a/Makefile.test +++ b/Makefile.test @@ -4,15 +4,15 @@ ifndef PROJ_DIR PROJ_DIR := ../../ endif -IVFLAGS += -I$(PROJ_DIR)/include/ -DSIMULATION +def : test + +include $(PROJ_DIR)/Makefile.util + +IVFLAGS += -DSIMULATION # The macroassembly header file is somewhat different thing, but I don't know # what place would be more suitable for it than include/ dir MACROASM_FLAGS += -I$(PROJ_DIR)/include/ -E -include $(PROJ_DIR)/Makefile.config -include $(PROJ_DIR)/Makefile.util -include $(PROJ_DIR)/tools/Makefile.tools - ifdef DEBUG IVFLAGS += -DDEBUG DBG&SAVE = tee "$(1)" @@ -20,9 +20,6 @@ else DBG&SAVE = cat > "$(1)" # putting cat through pipe - what an animal cruelty! endif -vpath %.v $(PROJ_DIR):$(PROJ_DIR)/design/:$(PROJ_DIR)/models/:. -vpath %.vh $(PROJ_DIR)/include:. - ifdef QUICK_TEST ifdef VGA_TEST SKIPPING = 1 @@ -43,11 +40,6 @@ ifdef VGA_TEST endif endif -TOOLS_TARGETS = $(addprefix $(PROJ_DIR)/tools/,$(TOOLS)) - -$(TOOLS_TARGETS) : $(PROJ_DIR)/% : - $(MAKE) -C $(PROJ_DIR) $* - %.mem : %.memv $(IV) $(MACROASM_FLAGS) $^ -o $@ @@ -59,21 +51,16 @@ ifdef VGA_TEST report.log VGAdump.mem : $(PROJ_DIR)/design/font.mem endif report.log VGAdump.mem : test.vvp - vvp $< | $(call DBG&SAVE,report.log) + $(VVP) $< | $(call DBG&SAVE,report.log) VGAdump.ppm : $(PROJ_DIR)/tools/VGAdump2ppm VGAdump.mem grep -v // < VGAdump.mem | $< > $@ -GENERATED_MEM_FILES := $(shell find . -name "*.s.tcl") -GENERATED_MEM_FILES := $(basename $(basename $(GENERATED_MEM_FILES))) -GENERATED_MEM_FILES += $(basename $(shell find . -name "*.memv")) -GENERATED_MEM_FILES += $(basename $(shell find . -name "*.wat")) -GENERATED_MEM_FILES := $(addsuffix .mem,$(GENERATED_MEM_FILES)) - clean : - rm $(GENERATED_MEM_FILES) *.vvp *.wasm report.log VGAdump.mem \ + find . -name "*.vvp" -delete + rm $(call FIND_GENERATED_FILES,.) report.log VGAdump.mem \ VGAdump.ppm 2>/dev/null || true -.PHONY : test clean $(TOOLS_TARGETS) +.PHONY : test def clean $(TOOLS_TARGETS) .SECONDARY : $(TOOLS_TARGETS) diff --git a/Makefile.util b/Makefile.util index 02ad5a3..4abddca 100644 --- a/Makefile.util +++ b/Makefile.util @@ -1,4 +1,31 @@ -FILE_LINES = `grep -E '^[[:space:]]*[^[:space:]/]' -c $(1)` +ifndef PROJ_DIR +PROJ_DIR := ./ +endif + +include $(PROJ_DIR)/Makefile.config + +IVFLAGS += -I$(PROJ_DIR)/include/ + +vpath %.v $(PROJ_DIR)/design/:$(PROJ_DIR)/models/:$(PROJ_DIR)/examples/:. +vpath %.vh $(PROJ_DIR)/include:. +vpath %.pcf $(PROJ_DIR):. + +FILE_LINES = $(shell grep -E '^[[:space:]]*[^[:space:]/]' -c $(1)) + +design.json yosys.log : design.v + $(YOSYS) -p 'read_verilog -defer $<' \ + -p 'synth_ice40 -top $(TOPMODULE) -json design.json' \ + > yosys.log 2>&1 + +design.asc pnr.log: $(PCF) design.json + $(PNR) --hx8k --asc design.asc --pcf $< --json design.json \ + --package ct256 > pnr.log 2>&1 + +design.bin : design.asc + $(ICEPACK) $< $@ + +prog : design.bin + sudo iceprogduino $< %.mem : $(PROJ_DIR)/tclasm.tcl %.s.tcl tclsh $^ > $@ @@ -8,3 +35,36 @@ FILE_LINES = `grep -E '^[[:space:]]*[^[:space:]/]' -c $(1)` %.wasm : %.wat $(WAT2WASM) $< -o $@ + +include $(PROJ_DIR)/tools/Makefile.tools + +TOOLS_TARGETS = $(addprefix $(PROJ_DIR)/tools/,$(TOOLS)) + +$(TOOLS_TARGETS) : $(PROJ_DIR)/tools/% : + $(MAKE) -C $(dir $@) $* + +FIND_TCLASM_BASE_NAMES = \ + $(basename $(basename $(shell find $(1) -name "*.s.tcl"))) + +FIND_WAT_BASE_NAMES = \ + $(basename $(shell find $(1) -name "*.wat")) + +FIND_MEMV_BASE_NAMES = \ + $(basename $(shell find $(1) -name "*.memv")) + +FIND_GENERATED_MEM_BASE_NAMES = \ + $(call FIND_TCLASM_BASE_NAMES,$(1)) \ + $(call FIND_WAT_BASE_NAMES,$(1)) \ + $(call FIND_MEMV_BASE_NAMES,$(1)) + +FIND_GENERATED_MEM_FILES = \ + $(addsuffix .mem,$(call FIND_GENERATED_MEM_BASE_NAMES,$(1))) + +FIND_GENERATED_WASM_FILES = \ + $(addsuffix .wasm,$(call FIND_WAT_BASE_NAMES,$(1))) + +FIND_GENERATED_FILES = \ + $(call FIND_GENERATED_MEM_FILES,$(1)) \ + $(call FIND_GENERATED_WASM_FILES,$(1)) + +.PHONY : prog diff --git a/design/soc.v b/design/soc.v index 9b69133..7bf6721 100644 --- a/design/soc.v +++ b/design/soc.v @@ -29,14 +29,26 @@ `default_nettype none `ifndef ROM_WORDS_COUNT - `error_ROM_WORDS_COUNT_must_be_defined + `ifndef SIMULATION + `error_ROM_WORDS_COUNT_must_be_defined ; /* Cause syntax error */ + `endif + `define ROM_WORDS_COUNT "whatever" +`endif + +`ifndef FONT_FILE + `define FONT_FILE "design/font.mem" +`endif + +`ifndef EMBEDDED_ROM_FILE + `define EMBEDDED_ROM_FILE "design/rom.mem" `endif module soc #( - parameter FONT_FILE = "design/font.mem", - parameter ROM_FILE = "design/rom.mem" + parameter FONT_FILE = `FONT_FILE, + parameter ROM_WORDS_COUNT = `ROM_WORDS_COUNT, + parameter ROM_FILE = `EMBEDDED_ROM_FILE ) ( input wire clock_100mhz, @@ -133,7 +145,7 @@ module soc embedded_bram_slave #( .MEMORY_BLOCKS(2), - .WORDS_TO_INITIALIZE(`ROM_WORDS_COUNT), + .WORDS_TO_INITIALIZE(ROM_WORDS_COUNT), .INITIAL_CONTENTS_FILE(ROM_FILE) ) slave0 ( diff --git a/examples/example1_blink_led/Makefile b/examples/example1_blink_led/Makefile new file mode 100644 index 0000000..9755f33 --- /dev/null +++ b/examples/example1_blink_led/Makefile @@ -0,0 +1,3 @@ +SIMFLAGS += -DFINISH_ON_LED1=1 -DFINISH_ON_LED2=0 + +include ../../Makefile.example diff --git a/examples/example1_blink_led/instructions.s.tcl b/examples/example1_blink_led/instructions.s.tcl new file mode 100644 index 0000000..13c51e2 --- /dev/null +++ b/examples/example1_blink_led/instructions.s.tcl @@ -0,0 +1,57 @@ +## adapted from soc_measure_time test + +## we're going to write numbers from 0 to 639 at addresses h100000 to h1009FC +## and then write non-zero value at h100A00 + +# this will translate to 2 16-bit instructions +set_sp h100000 + +## load current value of timer, in a loop +## this is address 4 we later jump to +# this will translate to 2 16-bit instructions +loadwzx h1C0008 + +## loop until timer exceeds 500 +# this will translate to 2 16-bit instructions +const 500 +# this will translate to 1 16-bit instruction +lt +# this will translate to 1 16-bit instruction +cond_jump 4 + +## now, light led2 +# this will translate to 1 16-bit instruction +const 1 +# this will translate to 2 16-bit instructions +storew h1C0006 + +## second loop, analogous to the first one +## this is address 22 we later jump to +# this will translate to 2 16-bit instructions +loadwzx h1C0008 + +## loop until timer exceeds 1000 +# this will translate to 2 16-bit instructions +const 1000 +# this will translate to 1 16-bit instruction +lt +# this will translate to 1 16-bit instruction +cond_jump 22 + +## now, switch led2 off +# this will translate to 1 16-bit instruction +const 0 +# this will translate to 2 16-bit instructions +storew h1C0006 + +## third loop, analogous to the first two +## this is address 40 we later jump to +loadwzx h1C0008 + +## loop until timer exceeds 1500 +const 1500 +lt +cond_jump 40 + +## finish operation (will also put led1 on) +halt diff --git a/examples/example_toplevel.v b/examples/example_toplevel.v new file mode 100644 index 0000000..1da1750 --- /dev/null +++ b/examples/example_toplevel.v @@ -0,0 +1,142 @@ +`default_nettype none +`timescale 1ns/1ns + +`include "messages.vh" + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +`ifndef ROM_WORDS_COUNT + `error_ROM_WORDS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef EMBEDDED_ROM_FILE + `error_EMBEDDED_ROM_FILE_not_defined +; /* Cause syntax error */ +`endif + +`ifndef FONT_FILE + `error_FONT_FILE_not_defined +; /* Cause syntax error */ +`endif + +`ifndef FINISH_ON_IMAGE_WRITES + `define FINISH_ON_IMAGE_WRITES 0 +`else + `define FINISH_RULE_PROVIDED 1 +`endif + +`ifndef FINISH_ON_LED1 + `define FINISH_ON_LED1 -1 +`else + `define FINISH_RULE_PROVIDED 1 +`endif + +`ifndef FINISH_ON_LED2 + `define FINISH_ON_LED2 -1 +`else + `define FINISH_RULE_PROVIDED 1 +`endif + +`ifndef FINISH_RULE_PROVIDED + `define FINISH_RULE_PROVIDED 0 +`endif + +`ifndef MIN_TIME_NS + `define MIN_TIME_NS 1000 +`endif + +`ifndef MAX_TIME_NS + `define MAX_TIME_NS 250_000_000 +`endif + +module example(); + wire [9:0] image_writes; + wire can_finish; + + reg clock_100mhz; + reg reset; + + wire led1; + wire led2; + + soc_with_peripherals + #( + .FONT_FILE(`FONT_FILE), + .EMBEDDED_ROM_WORDS_COUNT(`ROM_WORDS_COUNT), + .EMBEDDED_ROM_FILE(`EMBEDDED_ROM_FILE) + ) soc + ( + .clock_100mhz(clock_100mhz), + + .button1(!reset), + .button2(1'b1), + + .led1(led1), + .led2(led2), + + .image_writes(image_writes) + ); + + integer i; + + initial begin + reset <= 1; + clock_100mhz <= 0; + + if (!`FINISH_RULE_PROVIDED) begin + `MSG(("No finish rule provided, simulation will terminate after %0d ns,", + `MAX_TIME_NS)); + end + + for (i = 0; i < `MAX_TIME_NS; i = i + 5) begin + #5; + + if (clock_100mhz) + reset <= 0; + + clock_100mhz <= ~clock_100mhz; + end + + `MSG(("%0d ns passed, finishing", `MAX_TIME_NS)); + $finish; + end + + assign can_finish = i >= `MIN_TIME_NS; + + always @ (led1) begin + if (i > 0) begin + if (!led1) + `MSG(("LED1 goes on, stack machine finished operation")); + else + `MSG(("LED1 goes off, stack machine resets")); + end + end + + always @ (led2) begin + if (i > 35) begin + if (!led2) + `MSG(("LED2 goes on")); + else + `MSG(("LED2 goes off")); + end + end + + generate + if (`FINISH_RULE_PROVIDED) begin + always @ (image_writes or led1 or led2 or can_finish) begin + if ((image_writes >= `FINISH_ON_IMAGE_WRITES) && + (`FINISH_ON_LED1 < 0 || `FINISH_ON_LED1 == !led1) && + (`FINISH_ON_LED2 < 0 || `FINISH_ON_LED2 == !led2) && + can_finish) begin + #1; + `MSG(("finishing")); + $finish; + end + end + end // if (`FINISH_RULE_PROVIDED) + endgenerate +endmodule // example diff --git a/models/flash_memory.v b/models/flash_memory.v index 3b6c659..43d6c99 100644 --- a/models/flash_memory.v +++ b/models/flash_memory.v @@ -63,8 +63,13 @@ module W25Q16BV_flash parameter memory_size = 1024 * 1024 * 2; /* 2 megabytes */ reg [7:0] memory [memory_size - 1 : 0]; - initial - $readmemh(INITIAL_CONTENTS_FILE, memory, 0, BYTES_TO_INITIALIZE - 1); + + generate + if (BYTES_TO_INITIALIZE) begin + initial + $readmemh(INITIAL_CONTENTS_FILE, memory, 0, BYTES_TO_INITIALIZE - 1); + end + endgenerate always @ (posedge sck) begin if (!powered_up && power_up_time + power_up_wait_time < $time) begin diff --git a/models/soc_with_peripherals.v b/models/soc_with_peripherals.v index 975c002..40ee341 100644 --- a/models/soc_with_peripherals.v +++ b/models/soc_with_peripherals.v @@ -9,8 +9,10 @@ module soc_with_peripherals #( - parameter FONT_FILE = "../design/font.mem", - parameter EMBEDDED_ROM_FILE = "../design/rom.mem", + parameter DESIGN_DIR = "../../design/", + parameter FONT_FILE = {DESIGN_DIR, "font.mem"}, + parameter EMBEDDED_ROM_WORDS_COUNT = "error, rom words count not given", + parameter EMBEDDED_ROM_FILE = {DESIGN_DIR, "rom.mem"}, parameter SPI_ROM_WORDS_COUNT = 0, parameter SPI_ROM_FILE = "/dev/zero" ) @@ -79,6 +81,7 @@ module soc_with_peripherals soc #( .FONT_FILE(FONT_FILE), + .ROM_WORDS_COUNT(EMBEDDED_ROM_WORDS_COUNT), .ROM_FILE(EMBEDDED_ROM_FILE) ) soc ( diff --git a/tests/soc_measure_time/test.v b/tests/soc_measure_time/test.v index b4f1082..08b4fd5 100644 --- a/tests/soc_measure_time/test.v +++ b/tests/soc_measure_time/test.v @@ -8,6 +8,11 @@ ; /* Cause syntax error */ `endif +`ifndef ROM_WORDS_COUNT + `error_ROM_WORDS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + module soc_test(); wire [9:0] image_writes; @@ -20,6 +25,7 @@ module soc_test(); soc_with_peripherals #( .FONT_FILE("../../design/font.mem"), + .EMBEDDED_ROM_WORDS_COUNT(`ROM_WORDS_COUNT), .EMBEDDED_ROM_FILE("instructions.mem") ) soc ( diff --git a/tests/soc_print_number/test.v b/tests/soc_print_number/test.v index 75c2b36..170825e 100644 --- a/tests/soc_print_number/test.v +++ b/tests/soc_print_number/test.v @@ -8,6 +8,11 @@ ; /* Cause syntax error */ `endif +`ifndef ROM_WORDS_COUNT + `error_ROM_WORDS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + module soc_test(); wire [9:0] image_writes; @@ -20,6 +25,7 @@ module soc_test(); soc_with_peripherals #( .FONT_FILE("../../design/font.mem"), + .EMBEDDED_ROM_WORDS_COUNT(`ROM_WORDS_COUNT), .EMBEDDED_ROM_FILE("instructions.mem") ) soc ( diff --git a/tests/soc_simple_display/test.v b/tests/soc_simple_display/test.v index 75c2b36..170825e 100644 --- a/tests/soc_simple_display/test.v +++ b/tests/soc_simple_display/test.v @@ -8,6 +8,11 @@ ; /* Cause syntax error */ `endif +`ifndef ROM_WORDS_COUNT + `error_ROM_WORDS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + module soc_test(); wire [9:0] image_writes; @@ -20,6 +25,7 @@ module soc_test(); soc_with_peripherals #( .FONT_FILE("../../design/font.mem"), + .EMBEDDED_ROM_WORDS_COUNT(`ROM_WORDS_COUNT), .EMBEDDED_ROM_FILE("instructions.mem") ) soc ( -- cgit v1.2.3