From bdfaa7c9b2e2943910b6ebee522d06cb215411ab Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Thu, 16 Jul 2020 16:47:22 +0200 Subject: some comments around snapshotted button values --- src/example.v | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/example.v b/src/example.v index da0b43e..dd1798c 100644 --- a/src/example.v +++ b/src/example.v @@ -627,6 +627,10 @@ module on_button_write(input wire clock_50mhz, input wire [17:0] written_memory_base, input wire but ); + /* + * We use a reg to snapshot (and invert) the button signal (button2). + * If we didn't snapshot it, we'd get timing problems. + */ reg button_pressed; /* 0 - waiting for write, 1 - writing, 2 - write complete */ @@ -740,7 +744,19 @@ module top(input wire clock_100mhz, output wire sck, output wire ss_n ); + /* + * We use a reg to snapshot (and invert) the reset signal + * (actually button1). If we didn't snapshot it, we'd get + * timing problems + */ reg reset; + /* + * `initial` usually isn't synthesizable, but in case + * it is on some particular FPGA - we try to make use of it + */ + initial + reset <= 1; + reg err_disabled; reg clock_50mhz; -- cgit v1.2.3