From 96e4965c09bd41f11162120d6312f2aae7efe7ea Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Thu, 31 Dec 2020 17:59:37 +0100 Subject: Add Wishbone datasheets --- README.txt | 4 +- design/embedded_bram_slave.v | 43 +++++++++++++++++++ design/interface_wrapper.v | 8 +++- design/miscellaneous_slave.v | 34 ++++++++++++++- design/spi_slave.v | 87 +++++++++++++++++++++++++++++++++++++- design/sram_slave.v | 35 ++++++++++++++++ design/stack_machine.v | 76 ++++++++++++++++++++++++++++++++- design/vga.v | 91 ++++++++++++++++++++++++++++++++++++++-- design/wrapped_stack_machine.v | 79 +++++++++++++++++++++++++++++++--- models/master.v | 39 +++++++++++++++++ models/slave.v | 40 +++++++++++++++++- tests/stack_machine_store/test.v | 2 - 12 files changed, 518 insertions(+), 20 deletions(-) diff --git a/README.txt b/README.txt index c4e0c41..1eac24c 100644 --- a/README.txt +++ b/README.txt @@ -21,9 +21,7 @@ go this way, because: - I'd end up mostly copying other's code, ending up with a copy-paster's thesis... -I'm trying to use Wishbone pipelined interconnect for CPU and other components, -but right now I'm not yet claiming compatibility (at some point I will add -those datasheets...). +I'm using Wishbone pipelined interconnect for CPU and other components. WebAsm binary format was not designed for direct execution, so I'm instead creating a minimal stack machine, that would allow almost 1:1 translation of diff --git a/design/embedded_bram_slave.v b/design/embedded_bram_slave.v index 519c772..c6da4c6 100644 --- a/design/embedded_bram_slave.v +++ b/design/embedded_bram_slave.v @@ -2,6 +2,49 @@ * This is very similar to design/slave.v, although with 1 important difference * - it's meant to be synthesizable (and use iCE40HX8K's embedded RAM). */ + +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | (MEMORY_BLOCKS*256)x16-bit memory core | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | $clog2(MEMORY_BLOCKS) + 8 bits | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE (determined by memory primitive, | + * | | about 100 MHz in case of iCE40HX8K) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | | Circuit assumes the use of synchronous | + * | Special requirements | RAM with asynchronour read | + * | | inreffable by synthesis software. | + * |---------------------------------+-----------------------------------------| + * | | The MEMORY_BLOCKS parameter can be used | + * | | to decide the size of the memory. | + * | Additional information | Single block contains 256 16-bit | + * | | words. Address width changes | + * | | accordingly to memory size. | + */ + `default_nettype none `define ADDR_WIDTH ($clog2(MEMORY_BLOCKS) + 8) diff --git a/design/interface_wrapper.v b/design/interface_wrapper.v index ada4a3f..eb708d6 100644 --- a/design/interface_wrapper.v +++ b/design/interface_wrapper.v @@ -1,7 +1,11 @@ /* - * For now, this wrapper ignores SEL_O signals - we'll update it for - * byte-granular accesses later. + * This module transforms a Wishbone pipelined MASTER interface with 32-bit + * data port and 8-bit granularity into one with 16-bit data port and 16-bit + * granularity. It's just a wrapper, it is not considered a Wishbone SLAVE nor + * MASTER by itself (although it could be presented that way). See Wishbone + * datasheets of data interfaces in stack_machine.v and wrapped_stack_machine.v. */ + `default_nettype none module interface_wrapper diff --git a/design/miscellaneous_slave.v b/design/miscellaneous_slave.v index 7274db7..0be33f2 100644 --- a/design/miscellaneous_slave.v +++ b/design/miscellaneous_slave.v @@ -1,5 +1,36 @@ /* - * This wb slave controls buttons, LEDs (only one LED, actually) and timer. + * This wb slave controls a button, a LED and timer. + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | miscellaneous peripherals core | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 3 | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | * * Registers and their addresses: * button2 clicks - address 1 @@ -28,6 +59,7 @@ * very short or very long times, it might be justifiable to only read one half * of the timer. */ + `default_nettype none module miscellaneous_slave diff --git a/design/spi_slave.v b/design/spi_slave.v index a53d9d2..5c671aa 100644 --- a/design/spi_slave.v +++ b/design/spi_slave.v @@ -1,3 +1,87 @@ +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | SPI master core | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | $clog2(MEMORY_BLOCKS + 1) + 8 bits | + * |---------------------------------+-----------------------------------------| + * | | NONE (determined by SPI slave devices | + * | Clock frequency constraints | and connections to them and also by | + * | | memory primitive inferred) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | | Circuit assumes the use of synchronous | + * | Special requirements | RAM with asynchronour read | + * | | inreffable by synthesis software. | + * |---------------------------------+-----------------------------------------| + * | | The MEMORY_BLOCKS parameter can be used | + * | | to decide the size of module's data | + * | | transfer memory. SPI operations are | + * | | performed as follows: | + * | Additional information | * Bytes to send through MOSI are | + * | | written at the beginning of data | + * | | transfer memory. | + * | | * Number of bytes to send is | + * | | written to the "bytes_to_output" | + * | | register. | + * | | * Number of bytes to receive from | + * | | MISO afterwards is written to the | + * | | "bytes_to_recive" register. | + * | | * Operation is started by writing | + * | | any value to the "operating" | + * | | register. | + * | | Also see the memory map below. | + * | | The "operating" register can be | + * | | read at any time to check if an | + * | | SPI operation has finished. It | + * | | reads a non-zero value if and only | + * | | if the SPI operation is still | + * | | occuring. Register writes are not | + * | | possible during SPI operation. Any | + * | | such write will be stalled and will | + * | | complete after SPI operation | + * | | finishes. This behavior can be | + * | | exploited to wait for operation | + * | | completion. | + */ + +/* + * The memory map is as follows: + * h000 - (h100*MEMORY_BLOCKS)-1 - data transfer memory + * h100*MEMORY_BLOCKS - "bytes_to_output" reg + * (h100*MEMORY_BLOCKS)+1 - "bytes_to_receive" reg + * (h100*MEMORY_BLOCKS)+2 - (h100*MEMORY_BLOCKS)+3 - "operating" reg + * + * If MEMORY_BLOCKS is set to 1, this results in the following memory map: + * h000 - h0FF - data transfer memory + * h100 - "bytes_to_output" reg + * h101 - "bytes_to_receive" reg + * h102 - h103 - "operating" reg + * + * Accessing any half of the "operating" reg results in the same behavior. + * Accessing higher addresses than specified results in UNDEFINED behavior. + */ + `default_nettype none `define ADDR_WIDTH ($clog2(MEMORY_BLOCKS + 1) + 8) @@ -102,7 +186,8 @@ module spi_slave wire wb_mwrite_completes; wire wb_rwrite_completes; - assign wb_mread_completes = !(spi_read_memory[0] || initial_spi_read_memory) && + assign wb_mread_completes = !(spi_read_memory[0] || + initial_spi_read_memory) && wb_read_memory[0]; assign wb_rread_completes = wb_read_regs; /* can always read immediately */ diff --git a/design/sram_slave.v b/design/sram_slave.v index 718ef8a..420626d 100644 --- a/design/sram_slave.v +++ b/design/sram_slave.v @@ -1,3 +1,38 @@ +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | 262144x16-bit memory core (512 KB) | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 18-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE (determined by memory primitive, | + * | | about 100 MHz if using K6R4016V1D) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Circuit assumes the use of asynchronous | + * | | RAM primitive, e.g. K6R4016V1D. | + */ + `default_nettype none module sram_slave diff --git a/design/stack_machine.v b/design/stack_machine.v index 13e55c1..01ccb74 100644 --- a/design/stack_machine.v +++ b/design/stack_machine.v @@ -2,6 +2,81 @@ `include "messages.vh" +/* + * This module provides 2 Wishbone MASTER interfaces described below. + * CLK_I and RST_I signals are shared between those interfaces. + * Two interfaces can, but don't have to, be made to access the same memory map. + * Instructions interface never performs writes (its WE_O is hardwired to low). + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core data interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 32-bit | + * | Data port, granularity | 8-bit | + * | Data port, maximum operand size | 32-bit | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 21-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | D_ACK_I | ACK_I | + * | | D_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | D_DAT_I | DAT_I() | + * | WISHBONE signals | D_DAT_O | DAT_O() | + * | | D_SEL_O | SEL_O | + * | | D_STB_O | STB_O | + * | | D_CYC_O | CYC_O | + * | | D_WE_O | WE_O | + * | | RST_I | RST_I | + * | | D_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + * + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core instructions | + * | | interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | I_ACK_I | ACK_I | + * | | I_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | I_DAT_I | DAT_I() | + * | WISHBONE signals | I_DAT_O | DAT_O() | + * | | I_SEL_O | SEL_O | + * | | I_STB_O | STB_O | + * | | I_CYC_O | CYC_O | + * | | I_WE_O | WE_O | + * | | RST_I | RST_I | + * | | I_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + */ + module stack_machine_new ( /* Those 2 are supposed to be common for both wishbone interfaces */ @@ -20,7 +95,6 @@ module stack_machine_new /* Data interface */ input wire D_ACK_I, - input wire D_ERR_I, /* We'll start using it soon */ output reg [20:0] D_ADR_O, input wire [31:0] D_DAT_I, output reg [31:0] D_DAT_O, diff --git a/design/vga.v b/design/vga.v index e69907c..5e42866 100644 --- a/design/vga.v +++ b/design/vga.v @@ -1,9 +1,92 @@ +/* + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | VGA signal generator (640x480@60Hz) | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | SLAVE, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 11-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE (determined by memory primitive, | + * | | about 100 MHz in case of iCE40HX8K) | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | | Circuit assumes the use of synchronous | + * | Special requirements | RAM with asynchronour read | + * | | inreffable by synthesis software. | + * |---------------------------------+-----------------------------------------| + * | | Module provides a simple text mode, | + * | | that can be used to display 30 lines of | + * | | 80 characters each. Module can be used | + * | | as follows: | + * | Additional information | * ASCII values of characters to | + * | | display should be written to text | + * | | mode memory. | + * | | * A non-zero value should be | + * | | written to the "power-on" | + * | | register to start generating VGA | + * | | signal. | + * | | * Zero should be written to the | + * | | "power-on" register to stop | + * | | generating VGA output. | + * | | Also see the memory map below. | + * | | The "power-on" register can be | + * | | read at any time to check if VGA | + * | | output is being generated. It reads | + * | | a non-zero value if module is | + * | | operating and zero otherwise. | + * | | Each byte of the text mode memory | + * | | corresponds to one character on | + * | | video display. They are arranged by | + * | | rows, from up to down. I.e. writing | + * | | value 65 to the first 2 bytes of | + * | | text video memory shall result in | + * | | character "A" being printed in 2 | + * | | leftmost fields of the topmost line | + * | | of the display. Writing a byte | + * | | value outside ASCII range shall | + * | | result in a replacement character | + * | | being written. Text mode memory is | + * | | 2560 bytes big. The last 160 bytes | + * | | are not used by video display and | + * | | don't serve any special purpose. | + * | | The font used for ASCII characters | + * | | is defined in an external file and | + * | | can be substituted. | + */ + +/* + * The memory map is as follows: + * h000 - h4FF - VGA text memory + * h500 - VGA power-on reg + * + * Accessing higher addresses than specified results in UNDEFINED behavior. + */ + `default_nettype none - module vga - #( - parameter FONT_FILE = "font.mem" - ) +module vga + #( + parameter FONT_FILE = "font.mem" + ) ( output wire ACK_O, input wire CLK_I, diff --git a/design/wrapped_stack_machine.v b/design/wrapped_stack_machine.v index 984b641..2c0244a 100644 --- a/design/wrapped_stack_machine.v +++ b/design/wrapped_stack_machine.v @@ -1,7 +1,79 @@ /* * This is a version of stack machine with 16-bit data ports - * on *both* wishbone interfaces (data interface is wrapped). + * on *both* Wishbone interfaces (data interface is wrapped). + * CLK_I and RST_I signals are shared between interfaces. + * Two interfaces can, but don't have to, be made to access the same memory map. + * Instructions interface never performs writes (its WE_O is hardwired to low). + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core data interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | D_ACK_I | ACK_I | + * | | D_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | D_DAT_I | DAT_I() | + * | WISHBONE signals | D_DAT_O | DAT_O() | + * | | D_SEL_O | SEL_O | + * | | D_STB_O | STB_O | + * | | D_CYC_O | CYC_O | + * | | D_WE_O | WE_O | + * | | RST_I | RST_I | + * | | D_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + * + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core instructions | + * | | interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | I_ACK_I | ACK_I | + * | | I_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | I_DAT_I | DAT_I() | + * | WISHBONE signals | I_DAT_O | DAT_O() | + * | | I_SEL_O | SEL_O | + * | | I_STB_O | STB_O | + * | | I_CYC_O | CYC_O | + * | | I_WE_O | WE_O | + * | | RST_I | RST_I | + * | | I_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | */ + `default_nettype none module wrapped_stack_machine @@ -35,11 +107,10 @@ module wrapped_stack_machine ); wire D_RAW_ACK_I; - wire D_RAW_ERR_I; /* Not used yet, always low */ wire [20:0] D_RAW_ADR_O; wire [31:0] D_RAW_DAT_I; wire [31:0] D_RAW_DAT_O; - wire [3:0] D_RAW_SEL_O; /* Not used yet, always 4'hF */ + wire [3:0] D_RAW_SEL_O; wire D_RAW_STB_O; wire D_RAW_CYC_O; wire D_RAW_WE_O; @@ -62,7 +133,6 @@ module wrapped_stack_machine /* Data interface */ .D_ACK_I(D_RAW_ACK_I), - .D_ERR_I(D_RAW_ERR_I), .D_ADR_O(D_RAW_ADR_O), .D_DAT_I(D_RAW_DAT_I), .D_DAT_O(D_RAW_DAT_O), @@ -81,7 +151,6 @@ module wrapped_stack_machine .RST_I(RST_I), .RAW_ACK_I(D_RAW_ACK_I), - .RAW_ERR_I(D_RAW_ERR_I), .RAW_ADR_O(D_RAW_ADR_O), .RAW_DAT_I(D_RAW_DAT_I), .RAW_DAT_O(D_RAW_DAT_O), diff --git a/models/master.v b/models/master.v index fbcb197..e23474a 100644 --- a/models/master.v +++ b/models/master.v @@ -4,7 +4,46 @@ * It performs a sequence of wishbone writes, reads and waits based on contents * of provided .mem file. It prints error messages whenever the value it reads * if different from the one it expects. + * +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock MASTER model for test benches | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_I | ACK_I | + * | | ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | SEL_O | SEL_O | + * | | STB_O | STB_O | + * | | CYC_O | CYC_O | + * | | WE_O | WE_O | + * | | RST_I | RST_I | + * | | STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | */ + `default_nettype none `include "messages.vh" diff --git a/models/slave.v b/models/slave.v index ed12a73..87c0aa8 100644 --- a/models/slave.v +++ b/models/slave.v @@ -1,4 +1,42 @@ -/* A wishbone slave testing module (a "mock") */ +/* + * A Wishbone SLAVE testing module (a "mock") + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | mock memory model for test benches | + * |---------------------------------+-----------------------------------------| + * | | SLAVE, pipelined READ/WRITE | + * | Supported cycles | (WRITE ability can be disabled | + * | | through module parameter) | + * |---------------------------------+-----------------------------------------| + * | Data port, size | parametrizable (WORD_SIZE bytes) | + * | Data port, granularity | parametrizable | + * | | (WORD_SIZE/SEL_LINES bytes) | + * | Data port, maximum operand size | same as data port size | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | parametrizable (ADR_BITS bits) | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | ACK_O | ACK_O | + * | | ADR_I | ADR_I() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | DAT_I | DAT_I() | + * | WISHBONE signals | DAT_O | DAT_O() | + * | | STB_I | STB_I | + * | | WE_I | WE_I | + * | | RST_I | RST_I | + * | | STALL_O | STALL_O | + * |---------------------------------+-----------------------------------------| + * | Special requirements | Should only be used in simulation, | + * | | not synthesizable. | + */ + `default_nettype none `include "messages.vh" diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v index 61b80c8..9c7058f 100644 --- a/tests/stack_machine_store/test.v +++ b/tests/stack_machine_store/test.v @@ -32,7 +32,6 @@ module stack_machine_test(); wire MI_STALL_I; wire MD_ACK_I; - wire MD_ERR_I; wire [20:0] MD_ADR_O; wire [31:0] MD_DAT_I; wire [31:0] MD_DAT_O; @@ -85,7 +84,6 @@ module stack_machine_test(); /* Data interface */ .D_ACK_I(MD_ACK_I), - .D_ERR_I(MD_ERR_I), .D_ADR_O(MD_ADR_O), .D_DAT_I(MD_DAT_I), .D_DAT_O(MD_DAT_O), -- cgit v1.2.3