From 328982871bb894f70eecb7868b6b6019fed76472 Mon Sep 17 00:00:00 2001 From: Wojciech Kosior Date: Mon, 7 Sep 2020 17:41:49 +0200 Subject: rename intercon to slave_dispatcher (soc module will remporarily stop working from this commit on) --- Makefile | 10 +- design/intercon.v | 142 ---------------------- design/slave_dispatcher.v | 118 ++++++++++++++++++ tests/intercon/operations.memv | 63 ---------- tests/intercon/test.v | 216 --------------------------------- tests/slave_dispatcher/operations.memv | 63 ++++++++++ tests/slave_dispatcher/test.v | 209 +++++++++++++++++++++++++++++++ 7 files changed, 395 insertions(+), 426 deletions(-) delete mode 100644 design/intercon.v create mode 100644 design/slave_dispatcher.v delete mode 100644 tests/intercon/operations.memv delete mode 100644 tests/intercon/test.v create mode 100644 tests/slave_dispatcher/operations.memv create mode 100644 tests/slave_dispatcher/test.v diff --git a/Makefile b/Makefile index d1e6fdc..5d5405c 100644 --- a/Makefile +++ b/Makefile @@ -49,7 +49,7 @@ STACK_MACHINE_TESTS := \ TESTS := \ self \ self_32bit_word \ - intercon \ + slave_dispatcher \ div \ vga \ sram_slave \ @@ -147,10 +147,10 @@ tests/sram_slave/test.vvp : tests/sram_slave/operations.mem \ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ $(filter %.v,$^) -o $@ -tests/intercon/test.vvp : tests/intercon/operations.mem tests/intercon/test.v \ - models/slave.v models/master.v design/intercon.v \ - include/messages.vh - $(IV) $(IVFLAGS) -s intercon_test \ +tests/slave_dispatcher/test.vvp : tests/slave_dispatcher/operations.mem \ + tests/slave_dispatcher/test.v models/slave.v models/master.v \ + design/slave_dispatcher.v include/messages.vh + $(IV) $(IVFLAGS) -s slave_dispatcher_test \ -DMASTER_OPERATIONS_COUNT=$(call FILE_LINES,$<) \ $(filter %.v,$^) -o $@ diff --git a/design/intercon.v b/design/intercon.v deleted file mode 100644 index bf908af..0000000 --- a/design/intercon.v +++ /dev/null @@ -1,142 +0,0 @@ -`default_nettype none - -module intercon - ( - input wire CLK, - input wire RST, - - input wire S0_ACK_O, - output wire S0_CLK_I, - output wire [17:0] S0_ADR_I, - output wire [15:0] S0_DAT_I, - input wire [15:0] S0_DAT_O, - output wire S0_RST_I, - output wire S0_STB_I, - output wire S0_WE_I, - input wire S0_STALL_O, - - input wire S1_ACK_O, - output wire S1_CLK_I, - output wire [17:0] S1_ADR_I, - output wire [15:0] S1_DAT_I, - input wire [15:0] S1_DAT_O, - output wire S1_RST_I, - output wire S1_STB_I, - output wire S1_WE_I, - input wire S1_STALL_O, - - input wire S2_ACK_O, - output wire S2_CLK_I, - output wire [17:0] S2_ADR_I, - output wire [15:0] S2_DAT_I, - input wire [15:0] S2_DAT_O, - output wire S2_RST_I, - output wire S2_STB_I, - output wire S2_WE_I, - input wire S2_STALL_O, - - input wire S3_ACK_O, - output wire S3_CLK_I, - output wire [17:0] S3_ADR_I, - output wire [15:0] S3_DAT_I, - input wire [15:0] S3_DAT_O, - output wire S3_RST_I, - output wire S3_STB_I, - output wire S3_WE_I, - input wire S3_STALL_O, - - output wire M_ACK_I, - output wire M_CLK_I, - input wire [19:0] M_ADR_O, - input wire [15:0] M_DAT_O, - output wire [15:0] M_DAT_I, - output wire M_RST_I, - input wire M_STB_O, - input wire M_CYC_O, - input wire M_WE_O, - output wire M_STALL_I - ); - - wire [0:3] acks; - wire [0:3] stalls; - wire [15:0] datas [0:3]; - assign acks = {S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O}; - assign stalls = {S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O}; - assign datas[0] = S0_DAT_O; - assign datas[1] = S1_DAT_O; - assign datas[2] = S2_DAT_O; - assign datas[3] = S3_DAT_O; - - reg [1:0] commands_awaiting; - reg [1:0] slave_last_accessed; - - wire operation_requested; - wire working; - wire [1:0] slave_accessed; - wire slave_switch; - wire [1:0] commands_awaiting_next_tick; - assign operation_requested = M_STB_O && M_CYC_O; - assign working = commands_awaiting || operation_requested; - assign slave_accessed = commands_awaiting ? slave_last_accessed : - M_ADR_O[19:18]; - assign M_ACK_I = acks[slave_accessed] && working; - assign M_DAT_I = datas[slave_accessed]; - assign slave_switch = slave_accessed != M_ADR_O[19:18]; - assign M_STALL_I = stalls[slave_accessed] || slave_switch || - (commands_awaiting == 3 && !M_ACK_I); - assign commands_awaiting_next_tick - = commands_awaiting - M_ACK_I + (operation_requested && !M_STALL_I); - -`ifdef SIMULATION - /* anything could be latched here, this is just to avoid undefined values */ - initial begin - slave_last_accessed <= 0; - commands_awaiting <= 2; /* It is supposed to be driven low by RST */ - end -`endif - - always @ (posedge CLK) begin - slave_last_accessed <= slave_accessed; - - if (RST) - commands_awaiting <= 0; - else - commands_awaiting <= commands_awaiting_next_tick; - end - - assign S0_CLK_I = CLK; - assign S1_CLK_I = CLK; - assign S2_CLK_I = CLK; - assign S3_CLK_I = CLK; - assign M_CLK_I = CLK; - - assign S0_RST_I = RST; - assign S1_RST_I = RST; - assign S2_RST_I = RST; - assign S3_RST_I = RST; - assign M_RST_I = RST; - - assign S0_ADR_I = M_ADR_O[17:0]; - assign S1_ADR_I = M_ADR_O[17:0]; - assign S2_ADR_I = M_ADR_O[17:0]; - assign S3_ADR_I = M_ADR_O[17:0]; - - assign S0_DAT_I = M_DAT_O; - assign S1_DAT_I = M_DAT_O; - assign S2_DAT_I = M_DAT_O; - assign S3_DAT_I = M_DAT_O; - - wire pass_strobe; - assign pass_strobe = operation_requested && !slave_switch && - (commands_awaiting != 3 || M_ACK_I); - - assign S0_STB_I = slave_accessed == 0 && pass_strobe; - assign S1_STB_I = slave_accessed == 1 && pass_strobe; - assign S2_STB_I = slave_accessed == 2 && pass_strobe; - assign S3_STB_I = slave_accessed == 3 && pass_strobe; - - assign S0_WE_I = M_WE_O; - assign S1_WE_I = M_WE_O; - assign S2_WE_I = M_WE_O; - assign S3_WE_I = M_WE_O; -endmodule // intercon diff --git a/design/slave_dispatcher.v b/design/slave_dispatcher.v new file mode 100644 index 0000000..8cd0022 --- /dev/null +++ b/design/slave_dispatcher.v @@ -0,0 +1,118 @@ +`default_nettype none + +module slave_dispatcher + ( + input wire CLK, + input wire RST, + + input wire S0_ACK_O, + output wire [17:0] S0_ADR_I, + output wire [15:0] S0_DAT_I, + input wire [15:0] S0_DAT_O, + output wire S0_STB_I, + output wire S0_WE_I, + input wire S0_STALL_O, + + input wire S1_ACK_O, + output wire [17:0] S1_ADR_I, + output wire [15:0] S1_DAT_I, + input wire [15:0] S1_DAT_O, + output wire S1_STB_I, + output wire S1_WE_I, + input wire S1_STALL_O, + + input wire S2_ACK_O, + output wire [17:0] S2_ADR_I, + output wire [15:0] S2_DAT_I, + input wire [15:0] S2_DAT_O, + output wire S2_STB_I, + output wire S2_WE_I, + input wire S2_STALL_O, + + input wire S3_ACK_O, + output wire [17:0] S3_ADR_I, + output wire [15:0] S3_DAT_I, + input wire [15:0] S3_DAT_O, + output wire S3_STB_I, + output wire S3_WE_I, + input wire S3_STALL_O, + + output wire S_COMBINED_ACK_O, + input wire [19:0] S_COMBINED_ADR_I, + input wire [15:0] S_COMBINED_DAT_O, + output wire [15:0] S_COMBINED_DAT_I, + input wire S_COMBINED_STB_I, + input wire S_COMBINED_WE_I, + output wire S_COMBINED_STALL_O + ); + + wire [0:3] acks; + wire [0:3] stalls; + wire [15:0] datas [0:3]; + assign acks = {S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O}; + assign stalls = {S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O}; + assign datas[0] = S0_DAT_O; + assign datas[1] = S1_DAT_O; + assign datas[2] = S2_DAT_O; + assign datas[3] = S3_DAT_O; + + reg [1:0] commands_awaiting; + reg [1:0] slave_last_accessed; + + wire working; + wire [1:0] slave_accessed; + wire slave_switch; + wire [1:0] commands_awaiting_next_tick; + assign working = commands_awaiting || S_COMBINED_STB_I; + assign slave_accessed = commands_awaiting ? slave_last_accessed : + S_COMBINED_ADR_I[19:18]; + assign S_COMBINED_ACK_O = acks[slave_accessed] && working; + assign S_COMBINED_DAT_O = datas[slave_accessed]; + assign slave_switch = slave_accessed != S_COMBINED_ADR_I[19:18]; + assign S_COMBINED_STALL_O = stalls[slave_accessed] || slave_switch || + (commands_awaiting == 3 && !S_COMBINED_ACK_O); + assign commands_awaiting_next_tick + = commands_awaiting - S_COMBINED_ACK_O + + (S_COMBINED_STB_I && !S_COMBINED_STALL_O); + +`ifdef SIMULATION + /* anything could be latched here, this is just to avoid undefined values */ + initial begin + slave_last_accessed <= 0; + commands_awaiting <= 2; /* It is supposed to be driven low by RST */ + end +`endif + + always @ (posedge CLK) begin + slave_last_accessed <= slave_accessed; + + if (RST) + commands_awaiting <= 0; + else + commands_awaiting <= commands_awaiting_next_tick; + end + + assign S0_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S1_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S2_ADR_I = S_COMBINED_ADR_I[17:0]; + assign S3_ADR_I = S_COMBINED_ADR_I[17:0]; + + assign S0_DAT_I = S_COMBINED_DAT_I; + assign S1_DAT_I = S_COMBINED_DAT_I; + assign S2_DAT_I = S_COMBINED_DAT_I; + assign S3_DAT_I = S_COMBINED_DAT_I; + + wire pass_strobe; + assign pass_strobe = S_COMBINED_STB_I && !slave_switch && + (commands_awaiting != 3 || S_COMBINED_ACK_O); + + assign S0_STB_I = slave_accessed == 0 && pass_strobe; + assign S1_STB_I = slave_accessed == 1 && pass_strobe; + assign S2_STB_I = slave_accessed == 2 && pass_strobe; + assign S3_STB_I = slave_accessed == 3 && pass_strobe; + + assign S0_WE_I = S_COMBINED_WE_I; + assign S1_WE_I = S_COMBINED_WE_I; + assign S2_WE_I = S_COMBINED_WE_I; + assign S3_WE_I = S_COMBINED_WE_I; +endmodule // slave_dispatcher diff --git a/tests/intercon/operations.memv b/tests/intercon/operations.memv deleted file mode 100644 index 8785d5c..0000000 --- a/tests/intercon/operations.memv +++ /dev/null @@ -1,63 +0,0 @@ -`include "macroasm.vh" // look into macroasm.vh for more info - -// The beginning copied from self test, only 1st slave is being accessed. -`WRITE(00000, abcd) -`WAIT -`READ (00000, abcd) -`WRITE(00001, 1234) -`READ (00000, abcd) -`DESELECT -`DESELECT -`READ (00001, 1234) -`WRITE(01010, a2a2) -`WRITE(00001, 4321) -`READ (01010, a2a2) -`WAIT -`WAIT -`WAIT -`WAIT -`WAIT -`DESELECT -`DESELECT -`DESELECT -`WAIT -`DESELECT -`WAIT -`READ(00001, 4321) -// Here, instructions targetting other slaves start appearing. -// Go through all the slaves -`WRITE(40040, efef) -`WRITE(80002, 1f1f) -`WRITE(c00c0, 1d1d) -`READ (80002, 1f1f) -`READ (c00c0, 1d1d) -`READ (40040, efef) -`WAIT -`WAIT -// Make a sequence of commands to slave 3 (addresses c0000 - fffff) -`READ (c00c0, 1d1d) -`WRITE(c1111, 0022) -`READ (c00c0, 1d1d) -`WRITE(c0001, 0001) -`WRITE(c0002, 0002) -`READ (c0001, 0001) -`READ (c0002, 0002) -`READ (c0001, 0001) -`WRITE(c0003, 0003) -`WRITE(c0002, 2222) -`READ (c0002, 2222) -`READ (c0003, 0003) -`WRITE(fffff, 5555) -`READ (c1111, 0022) -// Put a single command to another slave in-between commands to slave 3 -`WRITE(4ffff, b6b6) -`READ (fffff, 5555) -`WRITE(eeeee, aaaa) -`READ (eeeee, aaaa) -// Let slave 3 take a breath now -`READ (4ffff, b6b6) -`DESELECT -// We made writes to c0002 and c0001, make sure corresponding addreses -// in other slaves were not overwritten by mistake -`READ (80002, 1f1f) -`READ (00001, 4321) diff --git a/tests/intercon/test.v b/tests/intercon/test.v deleted file mode 100644 index 1945f44..0000000 --- a/tests/intercon/test.v +++ /dev/null @@ -1,216 +0,0 @@ -`default_nettype none - -`include "messages.vh" - -`ifndef MASTER_OPERATIONS_COUNT - `error_MASTER_OPERATIONS_COUNT_must_be_defined -; /* Cause syntax error */ -`endif - -`ifndef SIMULATION - `error_SIMULATION_not_defined -; /* Cause syntax error */ -`endif - -module intercon_test(); - wire M_ACK_I; - wire M_CLK_I; - wire [19:0] M_ADR_O; - wire [15:0] M_DAT_I; - wire [15:0] M_DAT_O; - wire M_RST_I; - wire M_STB_O; - wire M_CYC_O; - wire M_WE_O; - wire M_STALL_I; - - wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; - wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; - wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; - wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; - wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; - wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; - wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; - wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; - wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; - - reg CLK; - reg RST; - - /* Non-wishbone */ - wire M_finished; - - master_model - #(.MASTER_NR(0), - .OPERATIONS_FILE("operations.mem"), - .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) - ) master - ( - .ACK_I(M_ACK_I), - .CLK_I(M_CLK_I), - .ADR_O(M_ADR_O), - .DAT_I(M_DAT_I), - .DAT_O(M_DAT_O), - .RST_I(M_RST_I), - .STB_O(M_STB_O), - .CYC_O(M_CYC_O), - .WE_O(M_WE_O), - .STALL_I(M_STALL_I), - - .finished(M_finished) - ); - - memory_slave_model - #( - .SLAVE_NR(0) - ) slave0 - ( - .ACK_O(S0_ACK_O), - .CLK_I(S0_CLK_I), - .ADR_I(S0_ADR_I), - .DAT_I(S0_DAT_I), - .DAT_O(S0_DAT_O), - .RST_I(S0_RST_I), - .STB_I(S0_STB_I), - .WE_I(S0_WE_I), - .STALL_O(S0_STALL_O) - ); - - memory_slave_model - #( - .SLAVE_NR(1) - ) slave1 - ( - .ACK_O(S1_ACK_O), - .CLK_I(S1_CLK_I), - .ADR_I(S1_ADR_I), - .DAT_I(S1_DAT_I), - .DAT_O(S1_DAT_O), - .RST_I(S1_RST_I), - .STB_I(S1_STB_I), - .WE_I(S1_WE_I), - .STALL_O(S1_STALL_O) - ); - - memory_slave_model - #( - .SLAVE_NR(2) - ) slave2 - ( - .ACK_O(S2_ACK_O), - .CLK_I(S2_CLK_I), - .ADR_I(S2_ADR_I), - .DAT_I(S2_DAT_I), - .DAT_O(S2_DAT_O), - .RST_I(S2_RST_I), - .STB_I(S2_STB_I), - .WE_I(S2_WE_I), - .STALL_O(S2_STALL_O) - ); - - memory_slave_model - #( - .SLAVE_NR(3) - ) slave3 - ( - .ACK_O(S3_ACK_O), - .CLK_I(S3_CLK_I), - .ADR_I(S3_ADR_I), - .DAT_I(S3_DAT_I), - .DAT_O(S3_DAT_O), - .RST_I(S3_RST_I), - .STB_I(S3_STB_I), - .WE_I(S3_WE_I), - .STALL_O(S3_STALL_O) - ); - - intercon intercon - ( - .CLK(CLK), - .RST(RST), - - .S0_ACK_O(S0_ACK_O), - .S0_CLK_I(S0_CLK_I), - .S0_ADR_I(S0_ADR_I), - .S0_DAT_I(S0_DAT_I), - .S0_DAT_O(S0_DAT_O), - .S0_RST_I(S0_RST_I), - .S0_STB_I(S0_STB_I), - .S0_WE_I(S0_WE_I), - .S0_STALL_O(S0_STALL_O), - - .S1_ACK_O(S1_ACK_O), - .S1_CLK_I(S1_CLK_I), - .S1_ADR_I(S1_ADR_I), - .S1_DAT_I(S1_DAT_I), - .S1_DAT_O(S1_DAT_O), - .S1_RST_I(S1_RST_I), - .S1_STB_I(S1_STB_I), - .S1_WE_I(S1_WE_I), - .S1_STALL_O(S1_STALL_O), - - .S2_ACK_O(S2_ACK_O), - .S2_CLK_I(S2_CLK_I), - .S2_ADR_I(S2_ADR_I), - .S2_DAT_I(S2_DAT_I), - .S2_DAT_O(S2_DAT_O), - .S2_RST_I(S2_RST_I), - .S2_STB_I(S2_STB_I), - .S2_WE_I(S2_WE_I), - .S2_STALL_O(S2_STALL_O), - - .S3_ACK_O(S3_ACK_O), - .S3_CLK_I(S3_CLK_I), - .S3_ADR_I(S3_ADR_I), - .S3_DAT_I(S3_DAT_I), - .S3_DAT_O(S3_DAT_O), - .S3_RST_I(S3_RST_I), - .S3_STB_I(S3_STB_I), - .S3_WE_I(S3_WE_I), - .S3_STALL_O(S3_STALL_O), - - .M_ACK_I(M_ACK_I), - .M_CLK_I(M_CLK_I), - .M_ADR_O(M_ADR_O), - .M_DAT_O(M_DAT_O), - .M_DAT_I(M_DAT_I), - .M_RST_I(M_RST_I), - .M_STB_O(M_STB_O), - .M_CYC_O(M_CYC_O), - .M_WE_O(M_WE_O), - .M_STALL_I(M_STALL_I) - ); - - integer i; - - initial begin - CLK <= 0; - RST <= 1; - - for (i = 0; i < 500; i++) begin - #1; - - CLK <= ~CLK; - - if (CLK) - RST <= 0; - - if (M_finished) - $finish; - - /* - * I should delete this debugging code, but from time to time - * it proves so handy, that I just can't do it :/ - */ - // if (!CLK) - // `DBG(({"M_CYC_O: %d M_STB_O: %d M_ACK_I: %d M_STALL_I: %d ", - // "sla: %d sa: %d ca: %d RST: %b"}, - // M_CYC_O, M_STB_O, M_ACK_I, M_STALL_I, - // intercon.slave_last_accessed, intercon.slave_accessed, - // intercon.commands_awaiting, intercon.RST)); - end - - $display("error: master hasn't finished its opertaions in 300 ticks"); - $finish; - end -endmodule // intercon_test diff --git a/tests/slave_dispatcher/operations.memv b/tests/slave_dispatcher/operations.memv new file mode 100644 index 0000000..8785d5c --- /dev/null +++ b/tests/slave_dispatcher/operations.memv @@ -0,0 +1,63 @@ +`include "macroasm.vh" // look into macroasm.vh for more info + +// The beginning copied from self test, only 1st slave is being accessed. +`WRITE(00000, abcd) +`WAIT +`READ (00000, abcd) +`WRITE(00001, 1234) +`READ (00000, abcd) +`DESELECT +`DESELECT +`READ (00001, 1234) +`WRITE(01010, a2a2) +`WRITE(00001, 4321) +`READ (01010, a2a2) +`WAIT +`WAIT +`WAIT +`WAIT +`WAIT +`DESELECT +`DESELECT +`DESELECT +`WAIT +`DESELECT +`WAIT +`READ(00001, 4321) +// Here, instructions targetting other slaves start appearing. +// Go through all the slaves +`WRITE(40040, efef) +`WRITE(80002, 1f1f) +`WRITE(c00c0, 1d1d) +`READ (80002, 1f1f) +`READ (c00c0, 1d1d) +`READ (40040, efef) +`WAIT +`WAIT +// Make a sequence of commands to slave 3 (addresses c0000 - fffff) +`READ (c00c0, 1d1d) +`WRITE(c1111, 0022) +`READ (c00c0, 1d1d) +`WRITE(c0001, 0001) +`WRITE(c0002, 0002) +`READ (c0001, 0001) +`READ (c0002, 0002) +`READ (c0001, 0001) +`WRITE(c0003, 0003) +`WRITE(c0002, 2222) +`READ (c0002, 2222) +`READ (c0003, 0003) +`WRITE(fffff, 5555) +`READ (c1111, 0022) +// Put a single command to another slave in-between commands to slave 3 +`WRITE(4ffff, b6b6) +`READ (fffff, 5555) +`WRITE(eeeee, aaaa) +`READ (eeeee, aaaa) +// Let slave 3 take a breath now +`READ (4ffff, b6b6) +`DESELECT +// We made writes to c0002 and c0001, make sure corresponding addreses +// in other slaves were not overwritten by mistake +`READ (80002, 1f1f) +`READ (00001, 4321) diff --git a/tests/slave_dispatcher/test.v b/tests/slave_dispatcher/test.v new file mode 100644 index 0000000..d29b05c --- /dev/null +++ b/tests/slave_dispatcher/test.v @@ -0,0 +1,209 @@ +`default_nettype none + +`include "messages.vh" + +`ifndef MASTER_OPERATIONS_COUNT + `error_MASTER_OPERATIONS_COUNT_must_be_defined +; /* Cause syntax error */ +`endif + +`ifndef SIMULATION + `error_SIMULATION_not_defined +; /* Cause syntax error */ +`endif + +module slave_dispatcher_test(); + reg CLK; + reg RST; + + wire M_ACK_I; + wire [19:0] M_ADR_O; + wire [15:0] M_DAT_I; + wire [15:0] M_DAT_O; + wire M_STB_O; + wire M_CYC_O; + wire M_WE_O; + wire M_STALL_I; + + wire S0_ACK_O, S1_ACK_O, S2_ACK_O, S3_ACK_O; + wire S0_CLK_I, S1_CLK_I, S2_CLK_I, S3_CLK_I; + wire [17:0] S0_ADR_I, S1_ADR_I, S2_ADR_I, S3_ADR_I; + wire [15:0] S0_DAT_I, S1_DAT_I, S2_DAT_I, S3_DAT_I; + wire [15:0] S0_DAT_O, S1_DAT_O, S2_DAT_O, S3_DAT_O; + wire S0_RST_I, S1_RST_I, S2_RST_I, S3_RST_I; + wire S0_STB_I, S1_STB_I, S2_STB_I, S3_STB_I; + wire S0_WE_I, S1_WE_I, S2_WE_I, S3_WE_I; + wire S0_STALL_O, S1_STALL_O, S2_STALL_O, S3_STALL_O; + + wire S_COMBINED_ACK_O; + wire [19:0] S_COMBINED_ADR_I; + wire [15:0] S_COMBINED_DAT_I; + wire [15:0] S_COMBINED_DAT_O; + wire S_COMBINED_STB_I; + wire S_COMBINED_WE_I; + wire S_COMBINED_STALL_O; + + /* Non-wishbone */ + wire M_finished; + + master_model + #(.MASTER_NR(0), + .OPERATIONS_FILE("operations.mem"), + .OPERATIONS_COUNT(`MASTER_OPERATIONS_COUNT) + ) master + ( + .ACK_I(M_ACK_I), + .CLK_I(CLK), + .ADR_O(M_ADR_O), + .DAT_I(M_DAT_I), + .DAT_O(M_DAT_O), + .RST_I(RST), + .STB_O(M_STB_O), + .CYC_O(M_CYC_O), + .WE_O(M_WE_O), + .STALL_I(M_STALL_I), + + .finished(M_finished) + ); + + memory_slave_model + #( + .SLAVE_NR(0) + ) slave0 + ( + .ACK_O(S0_ACK_O), + .CLK_I(CLK), + .ADR_I(S0_ADR_I), + .DAT_I(S0_DAT_I), + .DAT_O(S0_DAT_O), + .RST_I(RST), + .STB_I(S0_STB_I), + .WE_I(S0_WE_I), + .STALL_O(S0_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(1) + ) slave1 + ( + .ACK_O(S1_ACK_O), + .CLK_I(CLK), + .ADR_I(S1_ADR_I), + .DAT_I(S1_DAT_I), + .DAT_O(S1_DAT_O), + .RST_I(RST), + .STB_I(S1_STB_I), + .WE_I(S1_WE_I), + .STALL_O(S1_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(2) + ) slave2 + ( + .ACK_O(S2_ACK_O), + .CLK_I(CLK), + .ADR_I(S2_ADR_I), + .DAT_I(S2_DAT_I), + .DAT_O(S2_DAT_O), + .RST_I(RST), + .STB_I(S2_STB_I), + .WE_I(S2_WE_I), + .STALL_O(S2_STALL_O) + ); + + memory_slave_model + #( + .SLAVE_NR(3) + ) slave3 + ( + .ACK_O(S3_ACK_O), + .CLK_I(CLK), + .ADR_I(S3_ADR_I), + .DAT_I(S3_DAT_I), + .DAT_O(S3_DAT_O), + .RST_I(RST), + .STB_I(S3_STB_I), + .WE_I(S3_WE_I), + .STALL_O(S3_STALL_O) + ); + + slave_dispatcher dispatcher + ( + .CLK(CLK), + .RST(RST), + + .S0_ACK_O(S0_ACK_O), + .S0_ADR_I(S0_ADR_I), + .S0_DAT_I(S0_DAT_I), + .S0_DAT_O(S0_DAT_O), + .S0_STB_I(S0_STB_I), + .S0_WE_I(S0_WE_I), + .S0_STALL_O(S0_STALL_O), + + .S1_ACK_O(S1_ACK_O), + .S1_ADR_I(S1_ADR_I), + .S1_DAT_I(S1_DAT_I), + .S1_DAT_O(S1_DAT_O), + .S1_STB_I(S1_STB_I), + .S1_WE_I(S1_WE_I), + .S1_STALL_O(S1_STALL_O), + + .S2_ACK_O(S2_ACK_O), + .S2_ADR_I(S2_ADR_I), + .S2_DAT_I(S2_DAT_I), + .S2_DAT_O(S2_DAT_O), + .S2_STB_I(S2_STB_I), + .S2_WE_I(S2_WE_I), + .S2_STALL_O(S2_STALL_O), + + .S3_ACK_O(S3_ACK_O), + .S3_ADR_I(S3_ADR_I), + .S3_DAT_I(S3_DAT_I), + .S3_DAT_O(S3_DAT_O), + .S3_STB_I(S3_STB_I), + .S3_WE_I(S3_WE_I), + .S3_STALL_O(S3_STALL_O), + + .S_COMBINED_ACK_O(S_COMBINED_ACK_O), + .S_COMBINED_ADR_I(S_COMBINED_ADR_I), + .S_COMBINED_DAT_I(S_COMBINED_DAT_I), + .S_COMBINED_DAT_O(S_COMBINED_DAT_O), + .S_COMBINED_STB_I(S_COMBINED_STB_I), + .S_COMBINED_WE_I(S_COMBINED_WE_I), + .S_COMBINED_STALL_O(S_COMBINED_STALL_O) + ); + + assign M_ACK_I = S_COMBINED_ACK_O; + assign M_DAT_I = S_COMBINED_DAT_O; + assign M_STALL_I = S_COMBINED_STALL_O; + + assign S_COMBINED_ADR_I = M_ADR_O; + assign S_COMBINED_DAT_I = M_DAT_O; + assign S_COMBINED_STB_I = M_STB_O && M_CYC_O; + assign S_COMBINED_WE_I = M_WE_O; + + integer i; + + initial begin + CLK <= 0; + RST <= 1; + + for (i = 0; i < 500; i++) begin + #1; + + CLK <= ~CLK; + + if (CLK) + RST <= 0; + + if (M_finished) + $finish; + end + + $display("error: master hasn't finished its opertaions in 300 ticks"); + $finish; + end +endmodule // slave_dispatcher_test -- cgit v1.2.3