diff options
Diffstat (limited to 'design/wrapped_stack_machine.v')
| -rw-r--r-- | design/wrapped_stack_machine.v | 79 |
1 files changed, 74 insertions, 5 deletions
diff --git a/design/wrapped_stack_machine.v b/design/wrapped_stack_machine.v index 984b641..2c0244a 100644 --- a/design/wrapped_stack_machine.v +++ b/design/wrapped_stack_machine.v @@ -1,7 +1,79 @@ /* * This is a version of stack machine with 16-bit data ports - * on *both* wishbone interfaces (data interface is wrapped). + * on *both* Wishbone interfaces (data interface is wrapped). + * CLK_I and RST_I signals are shared between interfaces. + * Two interfaces can, but don't have to, be made to access the same memory map. + * Instructions interface never performs writes (its WE_O is hardwired to low). + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core data interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | D_ACK_I | ACK_I | + * | | D_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | D_DAT_I | DAT_I() | + * | WISHBONE signals | D_DAT_O | DAT_O() | + * | | D_SEL_O | SEL_O | + * | | D_STB_O | STB_O | + * | | D_CYC_O | CYC_O | + * | | D_WE_O | WE_O | + * | | RST_I | RST_I | + * | | D_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + * + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core instructions | + * | | interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | I_ACK_I | ACK_I | + * | | I_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | I_DAT_I | DAT_I() | + * | WISHBONE signals | I_DAT_O | DAT_O() | + * | | I_SEL_O | SEL_O | + * | | I_STB_O | STB_O | + * | | I_CYC_O | CYC_O | + * | | I_WE_O | WE_O | + * | | RST_I | RST_I | + * | | I_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | */ + `default_nettype none module wrapped_stack_machine @@ -35,11 +107,10 @@ module wrapped_stack_machine ); wire D_RAW_ACK_I; - wire D_RAW_ERR_I; /* Not used yet, always low */ wire [20:0] D_RAW_ADR_O; wire [31:0] D_RAW_DAT_I; wire [31:0] D_RAW_DAT_O; - wire [3:0] D_RAW_SEL_O; /* Not used yet, always 4'hF */ + wire [3:0] D_RAW_SEL_O; wire D_RAW_STB_O; wire D_RAW_CYC_O; wire D_RAW_WE_O; @@ -62,7 +133,6 @@ module wrapped_stack_machine /* Data interface */ .D_ACK_I(D_RAW_ACK_I), - .D_ERR_I(D_RAW_ERR_I), .D_ADR_O(D_RAW_ADR_O), .D_DAT_I(D_RAW_DAT_I), .D_DAT_O(D_RAW_DAT_O), @@ -81,7 +151,6 @@ module wrapped_stack_machine .RST_I(RST_I), .RAW_ACK_I(D_RAW_ACK_I), - .RAW_ERR_I(D_RAW_ERR_I), .RAW_ADR_O(D_RAW_ADR_O), .RAW_DAT_I(D_RAW_DAT_I), .RAW_DAT_O(D_RAW_DAT_O), |