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-rw-r--r--design/vga.v91
1 files changed, 87 insertions, 4 deletions
diff --git a/design/vga.v b/design/vga.v
index e69907c..5e42866 100644
--- a/design/vga.v
+++ b/design/vga.v
@@ -1,9 +1,92 @@
+/*
+ * | *WISHBONE DATASHEET* |
+ * |---------------------------------------------------------------------------|
+ * | *Description* | *Specification* |
+ * |---------------------------------+-----------------------------------------|
+ * | General description | VGA signal generator (640x480@60Hz) |
+ * |---------------------------------+-----------------------------------------|
+ * | Supported cycles | SLAVE, pipelined READ/WRITE |
+ * |---------------------------------+-----------------------------------------|
+ * | Data port, size | 16-bit |
+ * | Data port, granularity | 16-bit |
+ * | Data port, maximum operand size | 16-bit |
+ * | Data transfer ordering | Big endian and/or little endian |
+ * | Data transfer ordering | Undefined |
+ * | Address port, size | 11-bit |
+ * |---------------------------------+-----------------------------------------|
+ * | Clock frequency constraints | NONE (determined by memory primitive, |
+ * | | about 100 MHz in case of iCE40HX8K) |
+ * |---------------------------------+-----------------------------------------|
+ * | | *Signal name* | *WISHBONE Equiv.* |
+ * | |------------------+----------------------|
+ * | | ACK_O | ACK_O |
+ * | | ADR_I | ADR_I() |
+ * | Supported signal list and cross | CLK_I | CLK_I |
+ * | reference to equivalent | DAT_I | DAT_I() |
+ * | WISHBONE signals | DAT_O | DAT_O() |
+ * | | STB_I | STB_I |
+ * | | WE_I | WE_I |
+ * | | RST_I | RST_I |
+ * | | STALL_O | STALL_O |
+ * |---------------------------------+-----------------------------------------|
+ * | | Circuit assumes the use of synchronous |
+ * | Special requirements | RAM with asynchronour read |
+ * | | inreffable by synthesis software. |
+ * |---------------------------------+-----------------------------------------|
+ * | | Module provides a simple text mode, |
+ * | | that can be used to display 30 lines of |
+ * | | 80 characters each. Module can be used |
+ * | | as follows: |
+ * | Additional information | * ASCII values of characters to |
+ * | | display should be written to text |
+ * | | mode memory. |
+ * | | * A non-zero value should be |
+ * | | written to the "power-on" |
+ * | | register to start generating VGA |
+ * | | signal. |
+ * | | * Zero should be written to the |
+ * | | "power-on" register to stop |
+ * | | generating VGA output. |
+ * | | Also see the memory map below. |
+ * | | The "power-on" register can be |
+ * | | read at any time to check if VGA |
+ * | | output is being generated. It reads |
+ * | | a non-zero value if module is |
+ * | | operating and zero otherwise. |
+ * | | Each byte of the text mode memory |
+ * | | corresponds to one character on |
+ * | | video display. They are arranged by |
+ * | | rows, from up to down. I.e. writing |
+ * | | value 65 to the first 2 bytes of |
+ * | | text video memory shall result in |
+ * | | character "A" being printed in 2 |
+ * | | leftmost fields of the topmost line |
+ * | | of the display. Writing a byte |
+ * | | value outside ASCII range shall |
+ * | | result in a replacement character |
+ * | | being written. Text mode memory is |
+ * | | 2560 bytes big. The last 160 bytes |
+ * | | are not used by video display and |
+ * | | don't serve any special purpose. |
+ * | | The font used for ASCII characters |
+ * | | is defined in an external file and |
+ * | | can be substituted. |
+ */
+
+/*
+ * The memory map is as follows:
+ * h000 - h4FF - VGA text memory
+ * h500 - VGA power-on reg
+ *
+ * Accessing higher addresses than specified results in UNDEFINED behavior.
+ */
+
`default_nettype none
- module vga
- #(
- parameter FONT_FILE = "font.mem"
- )
+module vga
+ #(
+ parameter FONT_FILE = "font.mem"
+ )
(
output wire ACK_O,
input wire CLK_I,