diff options
Diffstat (limited to 'design/stack_machine.v')
| -rw-r--r-- | design/stack_machine.v | 76 |
1 files changed, 75 insertions, 1 deletions
diff --git a/design/stack_machine.v b/design/stack_machine.v index 13e55c1..01ccb74 100644 --- a/design/stack_machine.v +++ b/design/stack_machine.v @@ -2,6 +2,81 @@ `include "messages.vh" +/* + * This module provides 2 Wishbone MASTER interfaces described below. + * CLK_I and RST_I signals are shared between those interfaces. + * Two interfaces can, but don't have to, be made to access the same memory map. + * Instructions interface never performs writes (its WE_O is hardwired to low). + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core data interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ/WRITE | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 32-bit | + * | Data port, granularity | 8-bit | + * | Data port, maximum operand size | 32-bit | + * | Data transfer ordering | Little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 21-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | D_ACK_I | ACK_I | + * | | D_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | D_DAT_I | DAT_I() | + * | WISHBONE signals | D_DAT_O | DAT_O() | + * | | D_SEL_O | SEL_O | + * | | D_STB_O | STB_O | + * | | D_CYC_O | CYC_O | + * | | D_WE_O | WE_O | + * | | RST_I | RST_I | + * | | D_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + * + * + * | *WISHBONE DATASHEET* | + * |---------------------------------------------------------------------------| + * | *Description* | *Specification* | + * |---------------------------------+-----------------------------------------| + * | General description | stack machine core instructions | + * | | interface | + * |---------------------------------+-----------------------------------------| + * | Supported cycles | MASTER, pipelined READ | + * |---------------------------------+-----------------------------------------| + * | Data port, size | 16-bit | + * | Data port, granularity | 16-bit | + * | Data port, maximum operand size | 16-bit | + * | Data transfer ordering | Big endian and/or little endian | + * | Data transfer ordering | Undefined | + * | Address port, size | 20-bit | + * |---------------------------------+-----------------------------------------| + * | Clock frequency constraints | NONE | + * |---------------------------------+-----------------------------------------| + * | | *Signal name* | *WISHBONE Equiv.* | + * | |------------------+----------------------| + * | | I_ACK_I | ACK_I | + * | | I_ADR_O | ADR_O() | + * | Supported signal list and cross | CLK_I | CLK_I | + * | reference to equivalent | I_DAT_I | DAT_I() | + * | WISHBONE signals | I_DAT_O | DAT_O() | + * | | I_SEL_O | SEL_O | + * | | I_STB_O | STB_O | + * | | I_CYC_O | CYC_O | + * | | I_WE_O | WE_O | + * | | RST_I | RST_I | + * | | I_STALL_I | STALL_I | + * |---------------------------------+-----------------------------------------| + * | Special requirements | NONE | + */ + module stack_machine_new ( /* Those 2 are supposed to be common for both wishbone interfaces */ @@ -20,7 +95,6 @@ module stack_machine_new /* Data interface */ input wire D_ACK_I, - input wire D_ERR_I, /* We'll start using it soon */ output reg [20:0] D_ADR_O, input wire [31:0] D_DAT_I, output reg [31:0] D_DAT_O, |