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-rw-r--r--design/embedded_bram_slave.v43
1 files changed, 43 insertions, 0 deletions
diff --git a/design/embedded_bram_slave.v b/design/embedded_bram_slave.v
index 519c772..c6da4c6 100644
--- a/design/embedded_bram_slave.v
+++ b/design/embedded_bram_slave.v
@@ -2,6 +2,49 @@
* This is very similar to design/slave.v, although with 1 important difference
* - it's meant to be synthesizable (and use iCE40HX8K's embedded RAM).
*/
+
+/*
+ * | *WISHBONE DATASHEET* |
+ * |---------------------------------------------------------------------------|
+ * | *Description* | *Specification* |
+ * |---------------------------------+-----------------------------------------|
+ * | General description | (MEMORY_BLOCKS*256)x16-bit memory core |
+ * |---------------------------------+-----------------------------------------|
+ * | Supported cycles | SLAVE, pipelined READ/WRITE |
+ * |---------------------------------+-----------------------------------------|
+ * | Data port, size | 16-bit |
+ * | Data port, granularity | 16-bit |
+ * | Data port, maximum operand size | 16-bit |
+ * | Data transfer ordering | Big endian and/or little endian |
+ * | Data transfer ordering | Undefined |
+ * | Address port, size | $clog2(MEMORY_BLOCKS) + 8 bits |
+ * |---------------------------------+-----------------------------------------|
+ * | Clock frequency constraints | NONE (determined by memory primitive, |
+ * | | about 100 MHz in case of iCE40HX8K) |
+ * |---------------------------------+-----------------------------------------|
+ * | | *Signal name* | *WISHBONE Equiv.* |
+ * | |------------------+----------------------|
+ * | | ACK_O | ACK_O |
+ * | | ADR_I | ADR_I() |
+ * | Supported signal list and cross | CLK_I | CLK_I |
+ * | reference to equivalent | DAT_I | DAT_I() |
+ * | WISHBONE signals | DAT_O | DAT_O() |
+ * | | STB_I | STB_I |
+ * | | WE_I | WE_I |
+ * | | RST_I | RST_I |
+ * | | STALL_O | STALL_O |
+ * |---------------------------------+-----------------------------------------|
+ * | | Circuit assumes the use of synchronous |
+ * | Special requirements | RAM with asynchronour read |
+ * | | inreffable by synthesis software. |
+ * |---------------------------------+-----------------------------------------|
+ * | | The MEMORY_BLOCKS parameter can be used |
+ * | | to decide the size of the memory. |
+ * | Additional information | Single block contains 256 16-bit |
+ * | | words. Address width changes |
+ * | | accordingly to memory size. |
+ */
+
`default_nettype none
`define ADDR_WIDTH ($clog2(MEMORY_BLOCKS) + 8)