start anew

3 files changed, 180 insertions, 0 deletions

diff --git a/tests/stack_machine_store/instructions.s.tcl b/tests/stack_machine_store/instructions.s.tcl
new file mode 100755
index 0000000..ddc3a8e
--- /dev/null
+++ b/tests/stack_machine_store/instructions.s.tcl
@@ -0,0 +1,29 @@
+#!/usr/bin/env tclsh
+
+source tclasm.tcl
+
+### simple test - write value hDEADBEEF to address h3ABCD
+
+## get value hDEADBEEF into r1
+
+#                             DDDD EEEE AA
+# bits 31:22 of hDEADBEEF are 1101 1110 10
+_immediate im<<=b1101111010
+#                             AA DDDD BBBB E
+# bits 21:11 of hDEADBEEF are 10 1101 1011 1
+_immediate im<<=b10110110111
+#                            EEE EEEE FFFF
+# bits 10:0 of hDEADBEEF are 110 1110 1111
+_exchange_im im<<=b11011101111
+
+## get address h7579A into im
+
+#                          7777 5555 7
+# bits 19:11 of h7579A are 0111 0101 0
+_immediate im=b011101010
+#                         777 9999 AAAA
+# bits 10:0 of h7579A are 111 1001 1010
+store im<<=b11110011010
+
+## finish test
+halt
diff --git a/tests/stack_machine_store/test.v b/tests/stack_machine_store/test.v
new file mode 100644
index 0000000..4c2326a
--- /dev/null
+++ b/tests/stack_machine_store/test.v
@@ -0,0 +1,148 @@
+`default_nettype none
+
+`include "messages.vh"
+
+`ifndef SIMULATION
+ `error_SIMULATION_not_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef INSTRUCTIONS_COUNT
+ `error_INSTRUCTIONS_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+`ifndef WORDS_TO_VERIFY_COUNT
+ `error_WORDS_TO_VERIFY_COUNT_must_be_defined
+; /* Cause syntax error */
+`endif
+
+module stack_machine_test();
+   wire        M_ACK_I;
+   wire        M_CLK_I;
+   wire [19:0] M_ADR_O;
+   wire [15:0] M_DAT_I;
+   wire [15:0] M_DAT_O;
+   wire        M_RST_I;
+   wire        M_STB_O;
+   wire        M_CYC_O;
+   wire        M_WE_O;
+   wire        M_STALL_I;
+
+   wire        S_ACK_O;
+   wire        S_CLK_I;
+   wire [17:0] S_ADR_I;
+   wire [15:0] S_DAT_I;
+   wire [15:0] S_DAT_O;
+   wire        S_RST_I;
+   wire        S_STB_I;
+   wire        S_WE_I;
+   wire        S_STALL_O;
+
+   /* Non-wishbone */
+   wire        M_finished;
+
+   stack_machine stack_machine
+     (
+      .ACK_I(M_ACK_I),
+      .CLK_I(M_CLK_I),
+      .ADR_O(M_ADR_O),
+      .DAT_I(M_DAT_I),
+      .DAT_O(M_DAT_O),
+      .RST_I(M_RST_I),
+      .STB_O(M_STB_O),
+      .CYC_O(M_CYC_O),
+      .WE_O(M_WE_O),
+      .STALL_I(M_STALL_I),
+
+      .finished(M_finished)
+      );
+
+   memory_slave_model
+     #(
+       .SLAVE_NR(0),
+       .WRITABLE(1),
+       .WORDS_TO_INITIALIZE(`INSTRUCTIONS_COUNT),
+       .INITIAL_CONTENTS_FILE("instructions.mem")
+       ) slave 
+       (
+	.ACK_O(S_ACK_O),
+      	.CLK_I(S_CLK_I),
+	.ADR_I(S_ADR_I),
+	.DAT_I(S_DAT_I),
+	.DAT_O(S_DAT_O),
+      	.RST_I(S_RST_I),
+      	.STB_I(S_STB_I),
+      	.WE_I(S_WE_I),
+	.STALL_O(S_STALL_O)
+	);
+
+   reg 	       CLK;
+   reg 	       RST;
+
+   assign M_ACK_I = S_ACK_O;
+   assign M_CLK_I = CLK;
+   assign M_DAT_I = S_DAT_O;
+   assign M_RST_I = RST;
+   assign M_STALL_I = S_STALL_O;
+
+   assign S_CLK_I = CLK;
+   assign S_ADR_I = M_ADR_O[17:0]; /* Ignore 2 topmost bits */
+   assign S_DAT_I = M_DAT_O;
+   assign S_RST_I = RST;
+   assign S_STB_I = M_STB_O && M_CYC_O;
+   assign S_WE_I = M_WE_O;
+
+   integer     i, j;
+   reg [17:0]  address;
+   reg [15:0]  expected_value;
+
+   reg [19:0]  words_to_verify[`WORDS_TO_VERIFY_COUNT * 2 - 1 : 0];
+
+   initial begin
+      CLK <= 0;
+      RST <= 1;
+
+      for (i = 0; i < 1000; i++) begin
+	 #1;
+
+	 CLK <= ~CLK;
+
+	 if (CLK) begin
+	    RST <= 0;
+	    `DBG(({"step: %0d   just_received: %d   r0: h%x   ",
+	    	   "r1: h%x   im: %b   sp: h%x   atu: h%x   ia: %d"},
+	    	  stack_machine.step,
+	    	  stack_machine.instruction_just_received, stack_machine.r0,
+	    	  stack_machine.r1, stack_machine.im, stack_machine.sp,
+	    	  stack_machine.addr_to_use,
+	    	  stack_machine.immediate_addressing));
+	 end
+
+	 if (M_finished) begin
+	    $readmemh("words_to_verify.mem", words_to_verify,
+		      0, `WORDS_TO_VERIFY_COUNT * 2 - 1);
+
+	    for (j = 0; j < `WORDS_TO_VERIFY_COUNT; j++) begin
+	       /*
+		* Byte-grained addresses are used in CPU, and we also use
+		* them in tclasm opcodes and in files with words for
+		* verification. Slaves and wishbone address 16-bit words, not
+		* single bytes. We need to drop the lowest bit here.
+		*/
+	       address = words_to_verify[2 * j][19:1];
+	       expected_value = words_to_verify[2 * j + 1];
+	       if (slave.memory[address] !== expected_value) begin
+		  `MSG(("error: expected h%x at h%x, but got h%x",
+			expected_value, address, slave.memory[address]));
+	       end
+	    end
+
+	    $finish;
+	 end // if (M_finished)
+      end // for (i = 0; i < 1000; i++)
+
+      $display("error: cpu hasn't finished its operations in 500 ticks");
+      $finish;
+   end // initial begin
+endmodule // stack_machine_test
diff --git a/tests/stack_machine_store/words_to_verify.mem b/tests/stack_machine_store/words_to_verify.mem
new file mode 100644
index 0000000..9056a1b
--- /dev/null
+++ b/tests/stack_machine_store/words_to_verify.mem
@@ -0,0 +1,3 @@
+// address  value
+   7579A    BEEF
+   7579C    DEAD