reindent code

1 files changed, 33 insertions, 33 deletions

diff --git a/src/example.v b/src/example.v
index 0609d69..63ad7ed 100644
--- a/src/example.v
+++ b/src/example.v
@@ -1,28 +1,28 @@
 `default_nettype none
 
-  module hex_print(input wire [3:0] halfbyte,
-		   input wire [7:0]  x,
-		   input wire [15:0] y,
-
-		   output wire 	     pixel
-		   );
-   wire [0:7] 			     number_0 [15:0];
-   wire [0:7] 			     number_1 [15:0];
-   wire [0:7] 			     number_2 [15:0];
-   wire [0:7] 			     number_3 [15:0];
-   wire [0:7] 			     number_4 [15:0];
-   wire [0:7] 			     number_5 [15:0];
-   wire [0:7] 			     number_6 [15:0];
-   wire [0:7] 			     number_7 [15:0];
-   wire [0:7] 			     number_8 [15:0];
-   wire [0:7] 			     number_9 [15:0];
-
-   wire [0:7] 			     letter_A [15:0];
-   wire [0:7] 			     letter_B [15:0];
-   wire [0:7] 			     letter_C [15:0];
-   wire [0:7] 			     letter_D [15:0];
-   wire [0:7] 			     letter_E [15:0];
-   wire [0:7] 			     letter_F [15:0];
+module hex_print(input wire [3:0] halfbyte,
+		 input wire [7:0]  x,
+		 input wire [15:0] y,
+
+		 output wire 	   pixel
+		 );
+   wire [0:7] 			   number_0 [15:0];
+   wire [0:7] 			   number_1 [15:0];
+   wire [0:7] 			   number_2 [15:0];
+   wire [0:7] 			   number_3 [15:0];
+   wire [0:7] 			   number_4 [15:0];
+   wire [0:7] 			   number_5 [15:0];
+   wire [0:7] 			   number_6 [15:0];
+   wire [0:7] 			   number_7 [15:0];
+   wire [0:7] 			   number_8 [15:0];
+   wire [0:7] 			   number_9 [15:0];
+
+   wire [0:7] 			   letter_A [15:0];
+   wire [0:7] 			   letter_B [15:0];
+   wire [0:7] 			   letter_C [15:0];
+   wire [0:7] 			   letter_D [15:0];
+   wire [0:7] 			   letter_E [15:0];
+   wire [0:7] 			   letter_F [15:0];
 
    assign number_0[0]  = 8'b00000000;
    assign number_0[1]  = 8'b00011000;
@@ -315,13 +315,13 @@
 endmodule
 
 module vga_timing(input wire       clock_50mhz,
-		  input wire 	   reset,
+		  input wire reset,
 
-		  output reg 	   h_sync,
-		  output reg 	   v_sync,
-		  output reg 	   display_on,
-		  output reg 	   pixel_starting,
-		  output reg 	   row_starting);
+		  output reg h_sync,
+		  output reg v_sync,
+		  output reg display_on,
+		  output reg pixel_starting,
+		  output reg row_starting);
 
    parameter h_pixels = 640;
    parameter v_pixels = 480;
@@ -343,12 +343,12 @@ module vga_timing(input wire       clock_50mhz,
    parameter h_frame_end = h_active_video_start + h_pixels;
    parameter v_frame_end = v_active_video_start + v_pixels;
 
-   reg [9:0] 			   h_counter;
-   reg [9:0] 			   v_counter;
+   reg [9:0] 		     h_counter;
+   reg [9:0] 		     v_counter;
 
-   reg 				   divider; // 25MHz
+   reg 			     divider; // 25MHz
 
-   wire 			   display_on_next_tick;
+   wire 		     display_on_next_tick;
    assign display_on_next_tick =  (h_counter < h_frame_end - 1) &&
 				  (h_counter >= h_active_video_start - 1) &&
 				  (v_counter < v_frame_end) &&