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<title>AGH-engineering-thesis/tools/Makefile, branch master</title>
<subtitle>Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland</subtitle>
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<updated>2020-12-29T18:52:00Z</updated>
<entry>
<title>add a C program for translating binary files to format understood by Verilog</title>
<updated>2020-12-29T18:52:00Z</updated>
<author>
<name>Wojciech Kosior</name>
<email>kwojtus@protonmail.com</email>
</author>
<published>2020-12-29T18:52:00Z</published>
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<entry>
<title>initial work towards translating wasm to stack machine (with a provisional bench)</title>
<updated>2020-09-19T19:22:41Z</updated>
<author>
<name>Wojciech Kosior</name>
<email>kwojtus@protonmail.com</email>
</author>
<published>2020-09-19T19:22:41Z</published>
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