AGH-engineering-thesis/tests/embedded_bram_slave, branch master Code related to my engineering thesis at AGH University of Science and Technology in Kraków, Poland https://git.koszko.org/AGH-engineering-thesis/atom?h=master 2020-09-08T19:00:13Z enable slave and master models to use SEL_ signal 2020-09-08T19:00:13Z Wojciech Kosior kwojtus@protonmail.com 2020-09-08T19:00:13Z urn:sha1:bc43ceac936b48fdccfcac33e172e176273d504f remove trailing whitespace 2020-09-08T15:46:12Z Wojciech Kosior kwojtus@protonmail.com 2020-09-08T15:46:12Z urn:sha1:cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9c modernize the build (test) system 2020-09-08T15:27:48Z Wojciech Kosior kwojtus@protonmail.com 2020-09-08T15:27:48Z urn:sha1:cbc2686373a5fe81b6b28f845edc323d4cae56e5 treat embedded RAM as read-only in test bench 2020-09-03T18:23:13Z Wojciech Kosior kwojtus@protonmail.com 2020-09-03T18:23:13Z urn:sha1:9d76f0b02695c341a0d734b21b4eb8726bbc06fa add bench for embedded ram wishbone slave 2020-09-02T12:20:39Z Wojciech Kosior kwojtus@protonmail.com 2020-09-02T12:20:39Z urn:sha1:5cf95f5885033c04ce26c53a0e10e8f2636eac25