AGH-engineering-thesis/models, branch masterCode related to my engineering thesis at AGH University of Science and Technology in Kraków, Polandhttps://git.koszko.org/AGH-engineering-thesis/atom?h=master2020-12-31T16:59:37ZAdd Wishbone datasheets2020-12-31T16:59:37ZWojciech Kosiorkwojtus@protonmail.com2020-12-31T16:59:37Zurn:sha1:96e4965c09bd41f11162120d6312f2aae7efe7eaadd the ability to include additional data at the end of bitstream image and prepare an example, that reads thic data through SPI and displays it2020-12-29T18:56:04ZWojciech Kosiorkwojtus@protonmail.com2020-12-29T18:56:04Zurn:sha1:68c80359ba0983bc21a18c0270025be9b441c0bbprepare makefile infrastructure for writing examples2020-12-24T08:22:34ZWojciech Kosiorkwojtus@protonmail.com2020-12-24T08:22:34Zurn:sha1:f122fa70e30a7d7744b38fa22bd1d5aa949e8277incorporate SPI module into main design2020-11-03T21:01:29ZWojciech Kosiorkwojtus@protonmail.com2020-11-03T21:01:29Zurn:sha1:31347a54ac571ded6177b68e24aa2d0c2f2cab28add spi wishbone slave with a simplified flash memory chip model and a test bench2020-11-03T18:16:12ZWojciech Kosiorkwojtus@protonmail.com2020-11-03T18:16:12Zurn:sha1:cd0c787bcfc89a0a1e14f4404a59cb4697854621fix verification when SEL_O != 4'b11112020-09-09T20:22:50ZWojciech Kosiorkwojtus@protonmail.com2020-09-09T20:22:50Zurn:sha1:334f86ccc899b92e44f71f1ad85dcc3c31ef1a2cenable slave and master models to use SEL_ signal2020-09-08T19:00:13ZWojciech Kosiorkwojtus@protonmail.com2020-09-08T19:00:13Zurn:sha1:bc43ceac936b48fdccfcac33e172e176273d504fremove trailing whitespace2020-09-08T15:46:12ZWojciech Kosiorkwojtus@protonmail.com2020-09-08T15:46:12Zurn:sha1:cd0421f0c30fcbe557c89f0fe7cd1b1e5ea42f9creplace fixed-width constant from now-parameterized wb slave model2020-09-05T10:56:47ZWojciech Kosiorkwojtus@protonmail.com2020-09-05T10:56:47Zurn:sha1:b4e6d666a8c625e1c962312f7f2eb4cb54395dc7fix master after parametrization2020-09-04T15:22:40ZWojciech Kosiorkwojtus@protonmail.com2020-09-04T15:22:40Zurn:sha1:e724f3543ea145386ca02999346bc784ee6e448f